GENERAL DESCRIPTION

SAA7214 system overview

The device is part of a comprehensive source decoding kit which contains all the hardware and software required to receive and decode MPEG2 transport streams, including descrambling, demultiplexing. In addition, it includes a MIPS PR3001 RISC CPU core and several peripheral interfaces such as UARTs, I2C-bus units, and an IEEE 1284 (Centronics) interface. The SAA7214 is therefore capable of performing all controller tasks in digital television applications such as set-top boxes. The SAA7214 is compliant to DVB specification.

FEATURES

General features

• Conditional access descrambling DVB-compliant

• Stream demultiplexing (TS, PES, program and proprietary streams)

• Internal PR3001 32-bit RISC processor running at 40.5 MHz

• Low-power sleep modes supported across the chip

• Comprehensive driver software and development tool support

• Package: SQFP208.

The following sections specify the features in more detail, in the form of a feature matrix.

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APPLICATIONS

• Digital television decoder environment.