GENERAL DESCRIPTION

The PCD5042 DECT Burst Mode Controller (BMC) is a custom IC that performs the DECT Physical Layer and MAC Layer time-critical functions, for use in DECT base station products which comply with the following standards:

• DECT CI part 2: Physical layer (DE/RES 3001-2)

• DECT CI part 3 : Medium Access Control layer (DE/RES 3001-3)

• DECT CI part 7: Security features for DECT (DE/RES 3001-7)

• DECT CI part 9: Public Access Profile (DE/RES 3001-9).

The PCD5042 has interfaces to:

• Up to 4 ADPCM CODECs in a simple base station (with up to 4 analogue lines) without glue logic

• n x 64 kbits/s highway, where n = 1 to 32, for systems requiring more than 4 connections to the network

• A radio transceiver; the interface is fully decoded, and includes power-down signals

• An external microcontroller.

The PCD5042 is designed to be connected to an ADPCM CODEC (Philips’ PCD5032, for example) and an 80C51-type microcontroller. Other microcontrollers (e.g. 68000) and CODECs can also be supported.

FEATURES

• On-chip pre-programmed Communication Controller with embedded firmware for implementation of Traffic Bearer Control (TBC), MAC message handling, scanning, and control of the device’s other functional units.

• Fixed Part (FP) modes

• TDMA frame (de)multiplexing

• Encryption

• Scrambling

• CRC generation and checking

• Beacon transmission control (by P00 packets)

• On-chip comparator for receive data slicer function (only available in the LQFP80 package)

• Switches up to12 active speech channels from speech interface to 1152 kbits/s. radio interface, and vice versa

• Dual channel speech/data capability

• RSSI measurement, with on-chip 6-bits peak/hold detector

• Local call switching for up to 6 internal calls on RF side/local call switching on speech side.

• Quality control report

• Digital Phase Locked Loop (DPLL)

• Synchronization (handset to active bearer, base station to cluster of RFPs)

• Seamless handover procedure

• Fast (hardware) and slow (software) mute function

• 1 kbyte extended RAM memory

• On-chip crystal oscillator (13.824 MHz)

• Programmable microcontroller clock frequency

• Programmable interrupts

• Watchdog with two programmable time-outs

• Low power consumption in standby mode

• Low supply voltage (2.7 to 5.5 V)

• SACMOS technology