DESCRIPTION

The 74F598 consists of an 8–bit storage register feeding a parallel–in/serial–in, parallel–out/serial–out 8–bit shift register. Both the storage register and shift register have positive edge–triggered clocks. The shift register has asynchronous reset and when SHCP is Low, it has asynchronous load.

FEATURES

• High impedance PNP base input for reduced loading (20µA in High and Low states)

• 8–bit parallel storage register

• Shift register has asynchronous direct overriding reset

• Shift load SHLD is functional when SHCP is Low and locked out when SHCP is High.

• Guaranteed shift frequency DC to 105MHz

• Parallel 3–State I/O storage register inputs and shift register parallel outputs