DESCRIPTION

The 74F174 has six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output.

FEATURES

• Six edge-triggered D-type flip-flops

• Buffered common Clock

• Buffered, asynchronous Master Reset