DESCRIPTION

The 74AHC/AHCT377 D-type flip-flops are high-speed silicon-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A.

The 74AHC/AHCT377 devices have eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. A common clock (CP) input loads all flip-flops simultaneously when the data enable (E) is LOW. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop.

The E input must be stable only one set-up time prior to the LOW-to-HIGH transition for predictable operation.

FEATURES

• ESD protection:

HBM EIA/JESD22-A114-A exceeds 2000 V

MM EIA/JESD22-A115-A exceeds 200 V

CDM EIA/JESD22-C101 exceeds 1000 V

• Balanced propagation delays

• All inputs have Schmitt-trigger actions

• Inputs accept voltages higher than VCC

• Ideal for addressable register applications

• Data enable for address and data synchronization

• Eight positive-edge triggered D-type flip-flops

• See “273” for master reset version

• See “373” for transparent latch version

• See “374” for 3-state version

• For AHC only: operates with CMOS input levels

• For AHCT only: operates with TTL input levels

• Specified from −40 to +85 and from −40 to +125 °C.