Description

The PI90LVx386 family consists of sixteen differential line receivers with 3-state outputs that implement Low-Voltage Differential Signaling (LVDS). Any of the differential receivers will provide a valid logical output state with a ±100mV differential input voltage within the input common-mode voltage range that allows 0 to 3V of ground potential difference between two LVDS nodes. The independent EN pins can be used to place the outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In high-impedance state, outputs neither load nor drive the bus lines.

Features

• Sixteen line receivers meet or exceed the requirements of the ANSI TIA/EIA-644-1995 Standard

• Designed for signaling rates up to 660 Mbps

• 0V to 3V common-mode input voltage range

• Operates from a single 3.3V supply

• Typical propagation delay time: 2.6ns

• Output skew 100ps (typical)

• Part-to-part skew is less than 1ns

• Integrated 110-Ohm termination on PI90LVT386

• Low Voltage TTL (LVTTL) levels are 5V tolerant

• Open-circuit fail safe

• Flow-through pin out

• Packaging (Pb-free & Green available):

- 64-Pin Thin Shrink Small Output TSSOP (A)