Product Description

The PI6C2509-133 is a quiet, low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing low-noise clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to any clock output will be nearly zero. This zero-delay feature allows the CLK_IN input clock to be distributed, providing 5 clocks for the first bank, and an additional 4 clocks for the second bank.

Product Features

• Operating Frequency up to 150 MHz

• Low-Noise Phase-Locked Loop Clock Distribution to meet 133 MHz Registered DIMM Synchronous DRAM module specifications for server/workstation/PC applications

• Allows Clock Input to have Spread Spectrum modulation for EMI reduction

• Zero Input-to-output delay: Distribute One Clock Input to one bank of five and one bank of four outputs, with separate output enables

• Low jitter: Cycle-to-Cycle jitter –75ps max.

• On-chip series damping resistor at clock output drivers for low noise and EMI reduction

• Operates at 3.3V VCC

• Package: Plastic 24-pin TSSOP (L)