CMOS System Reset

Outline This IC is a system reset IC developed using the CMOS process. Super low consumption current of 0.25µA typ. has been achieved through use of the CMOS process. Also, detection voltage is high precision detection of ±2. Features 1. Super low consumption current 0.25µA typ. (when VDD

IC for CMOS System Reset

Outline This IC is a system reset IC developed using the CMOS process. Super low consumption current of 0.25µA typ. has been achieved through use of the CMOS process. Also, detection voltage is high precision detection of ±2. Features 1. Super low consumption current 0.25µA typ. (when VDD

CMOS system reset

Silicon planar type

Silicon planar type For stabilization of power supply ■ Features • Mini type package (3-pin) • Allowing to achieve a high-density set • Sharp rising performance • Wide voltage range: VZ = 2.0 V to 36 V

Silicon planar type

Silicon planar type For stabilization of power supply ■ Features • Mini type package (3-pin) • Allowing to achieve a high-density set • Sharp rising performance • Wide voltage range: VZ = 2.0 V to 36 V

Silicon planar type

Silicon planar type For stabilization of power supply ■ Features • Mini type package (3-pin) • Allowing to achieve a high-density set • Sharp rising performance • Wide voltage range: VZ = 2.0 V to 36 V

Silicon planar type

Silicon planar type For stabilization of power supply ■ Features • Mini type package (3-pin) • Allowing to achieve a high-density set • Sharp rising performance • Wide voltage range: VZ = 2.0 V to 36 V

PECL termination

DESCRIPTION Single channel, RC-type positive emitter-coupled logic (PECL) clock termination with integrated diodes, providing electrostatic discharge (ESD) protection up to 2 kV. Using thin film-on-silicon technology the PSSI3120CA integrates three resistors, one capacitor and two diodes in a SOT