Dual Serial Link, PHY Multiplexer

FEATURES • Integrated analog/digital device that interfaces a high-speed parallel bus to a high speed Low Voltage Differential Signal (LVDS) serial link with optional 1:1 protection. • For framers or modems without Utopia bus interfaces the S/UNI-DUPLEX provides cell delineation (I.432) across 1

DUAL SERIAL LINK PHY MULTIPLEXER

文件：1.97249 Mbytes Page：241 Pages

Dual Serial Link, PHY Multiplexer

文件：37.77 Kbytes Page：2 Pages

Dual Serial Link, PHY Multiplexer

文件：37.77 Kbytes Page：2 Pages

DUAL SERIAL LINK PHY MULTIPLEXER

文件：1.97249 Mbytes Page：241 Pages

150mA ULTRA-LOW QUIESCENT CURRENT LDO with ENABLE

Features Low VIN and Wide VIN Range: 2.0V to 5.25V Guarantee Output Current, 150mA Output Voltage Range: 1.2V to 4.5V VOUT Accuracy: ±1 Quiescent Current as Low as 0.25μA Typical Standby Current 0.02μA ESD Protection Exceeds JESD 22  Exceeds 4000V Human Body Model (A114)  Exceeds 400V M

Wire-Thread-Inserts

文件：102.37 Kbytes Page：3 Pages

Low Power Consumption LDO

文件：125.73 Kbytes Page：12 Pages

Common Mode Inductors/EMI Filters

文件：88.15 Kbytes Page：1 Pages

a step-down converter with integrated switching MOSFET

文件：338.49 Kbytes Page：9 Pages