18-Bit Universal Bus Driver with 3-State Outputs

Product Description Pericom Semiconductor’s PI74ALVC series of logic circuits are produced in the Company’s advanced 0.5 micron CMOS technology, achieving industry leading speed. The 18-bit PI74ALVC162835 universal bus driver is designed for 2.3V to 3.6V Vcc operation. Product Features • PI74AL

Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26??Series Resistors in Outputs

General Description The ALVC162835 low voltage 18-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. The ALVC162835 is designed with 26Ω series resistors in the outputs. This design reduces noise in applications suc

18-bit registered driver with 30ohm termination resistors (3-State)

DESCRIPTION The 74ALVC162835A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is LOW and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH tran

18-bit registered driver with 30 Ω termination resistors; 3-state

1 General description The 74ALVC162835A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is LOW and CP is held at LOW or HIGH, the data is latched; on the LOW

18-bit registered driver with 30 Ω termination resistors; 3-state

1 General description The 74ALVC162835A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is LOW and CP is held at LOW or HIGH, the data is latched; on the LOW

18-bit registered driver with 30ohm termination resistors (3-State)

DESCRIPTION The 74ALVC162835A is an 18-bit universal bus driver. Data flow is controlled by output enable (OE), latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is LOW and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH tran