Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs

Description The PI6C2510-133 is a “quiet,” low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high-frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input to

Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs

Description The PI6C2510-133E is a “enhanced,” low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input

Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs

Description The PI6C2510-133E is a “enhanced,” low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input

Low-Noise, Phase-Locked Loop Clock Driver with 10 Clock Outputs

Description The PI6C2510-133E is a “enhanced,” low-skew, low-jitter, phase-locked loop (PLL) clock driver, distributing high frequency clock signals for SDRAM and server applications. By connecting the feedback FB_OUT output to the feedback FB_IN input, the propagation delay from the CLK_IN input