Zero-Delay Clock Buffer

Description The PI6C2405A is a PLL based, zero-delay buffer, with the ability to distribute five outputs of up to 133MHz at 3.3V. All the outputs are distributed from a single clock input CLKIN and output OUT0 performs zero delay by connecting a feedback to PLL. An internal feedback on OUT0 is u

Zero-Delay Clock Buffer

Description The PI6C2405A is a PLL based, zero-delay buffer, with the ability to distribute five outputs of up to 133MHz at 3.3V. All the outputs are distributed from a single clock input CLKIN and output OUT0 performs zero delay by connecting a feedback to PLL. An internal feedback on OUT0 is u

Zero-Delay Clock Buffer

Description The PI6C2405A is a PLL based, zero-delay buffer, with the ability to distribute five outputs of up to 133MHz at 3.3V. All the outputs are distributed from a single clock input CLKIN and output OUT0 performs zero delay by connecting a feedback to PLL. An internal feedback on OUT0 is u

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC ZERO DELAY CLOCK BUFF SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：8-SOIC（0.154"，3.90mm 宽） 包装：管件 描述：IC ZERO DELAY CLOCK BUFF 8-SOIC 集成电路（IC） 时钟发生器，PLL，频率合成器

Zero-Delay Clock Buffer

Description The PI6C2405A is a PLL based, zero-delay buffer, with the ability to distribute five outputs of up to 133MHz at 3.3V. All the outputs are distributed from a single clock input CLKIN and output OUT0 performs zero delay by connecting a feedback to PLL. An internal feedback on OUT0 is u

Zero-Delay Clock Buffer

Description The PI6C2405A is a PLL based, zero-delay buffer, with the ability to distribute five outputs of up to 133MHz at 3.3V. All the outputs are distributed from a single clock input CLKIN and output OUT0 performs zero delay by connecting a feedback to PLL. An internal feedback on OUT0 is u

Zero-Delay Clock Buffer

Description The PI6C2405A is a PLL based, zero-delay buffer, with the ability to distribute five outputs of up to 133MHz at 3.3V. All the outputs are distributed from a single clock input CLKIN and output OUT0 performs zero delay by connecting a feedback to PLL. An internal feedback on OUT0 is u