丝印代码：00011100；PNP resistor-equipped transistor; R1 = 1 k廓, R2 = 1 k廓

文件：755.37 Kbytes Page：13 Pages

PNP resistor-equipped transistor; R1 = 1 kΩ, R2 = 1 kΩ

封装/外壳：3-XFDFN 包装：卷带（TR） 描述：TRANS PREBIAS PNP 50V DFN1006B-3 分立半导体产品 晶体管 - 双极（BJT）- 单，预偏置

PNP SILICON BIAS RESISTOR TRANSISTOR

This new series of digital transistors is designed to replace a single device and its external resistor bias network. The BRT (Bias Resistor Transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a base–emitter resistor. The

0.25關m Sea of Gates and Customer Structured Arrays

DESCRIPTION Oki’s 0.25µm Application-Specific Integrated Circuit (ASIC) products are available in both Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. Both the SOG-based MG115P series and the CSA-based MG75P series use a five-layer metal process on 0.25µm drawn (0.18µm L-eff

6-Pin DIP Optoisolators Darlington Output

6-Pin DIP Optoisolators Darlington Output The MTIL113 device consists of a gallium arsenide infrared emitting diode optically coupled to a monolithic silicon photodarlington detector. This device is designed for use in applications requiring high collector output currents at lower input currents

Reference Diode

文件：126.55 Kbytes Page：4 Pages

Reference Diode

文件：126.55 Kbytes Page：4 Pages