PDSP16256GC1R

The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 20MHz throughout in FFT and filter applications. Two PDSP16318As combined with a single PDSP16112A Complex Multiplier provide a compl

16 X 12 BIT COMPLEX MULTIPLIER

The PDSP16112/PDSP16112A will multply a complex (16+16) bit word by a complex (12+12) bit coefficient word and produce a complex (17+17) bit rounded product. FEATURES ■ 20MHz Complex Number (16+16) x (12+12) Multplication ■ Pipeline Architecture ■ Power Dissipation only 500mW ■ TTL Compatible

Complex Accumulator

The PDSP16318 contains two independent 20-bit Adder/Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 10MHz throughout in FFT and filter applications. Two PDSP16318s combined with a single PDSP16112A Complex Multiplier provide a complete

16 by 16 Bit Complex Multiplier

The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional twos complement. FEATURES ■ Complex Number (16 + 16) X (16 + 16) Multiplication ■ Full 32 bit Re

32K BUCKET BUFFER

The PDSP16540 Bucket Buffer is for use in systems which require a reservoir in which a block of data is accumulated, whilst previous data is being transferred to other system elements and then processed. It thus prevents the loss of incoming data whilst the previous block is being processed. Like

ALU and Barrel Shifter

文件：171.76 Kbytes Page：18 Pages

PDSP16256GC1R

Complex Accumulator

Pythagoras Processor

文件：89.6 Kbytes Page：8 Pages

Pythagoras Processor

文件：98.95 Kbytes Page：7 Pages

ALU and Barrel Shifter

文件：121.12 Kbytes Page：16 Pages

Complex Accumulator

The PDSP16318 contains two independent 20-bit Adder/Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 10MHz throughout in FFT and filter applications. Two PDSP16318s combined with a single PDSP16112A Complex Multiplier provide a complete

16 by 16 Bit Complex Multiplier

The PDSP16116A will multiply two complex (16 + 16) bit words every 50ns and can be configured to output the complete complex (32 + 32) bit result within a single cycle. The data format is fractional twos complement. FEATURES ■ Complex Number (16 + 16) X (16 + 16) Multiplication ■ Full 32 bit Re

PDSP16256GC1R

The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 20MHz throughout in FFT and filter applications. Two PDSP16318As combined with a single PDSP16112A Complex Multiplier provide a compl

PDSP16256GC1R

The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 20MHz throughout in FFT and filter applications. Two PDSP16318As combined with a single PDSP16112A Complex Multiplier provide a compl

Complex Accumulator

The PDSP16318 contains two independent 20-bit Adder/Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 10MHz throughout in FFT and filter applications. Two PDSP16318s combined with a single PDSP16112A Complex Multiplier provide a complete

PDSP16256GC1R

The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 20MHz throughout in FFT and filter applications. Two PDSP16318As combined with a single PDSP16112A Complex Multiplier provide a compl

PDSP16256GC1R

The PDSP16318/A contains two independent 20-bit Adder/Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 20MHz throughout in FFT and filter applications. Two PDSP16318As combined with a single PDSP16112A Complex Multiplier provide a compl

Complex Accumulator

The PDSP16318 contains two independent 20-bit Adder/Subtractors combined with accumulator registers and shift structures. The four port architecture permits full 10MHz throughout in FFT and filter applications. Two PDSP16318s combined with a single PDSP16112A Complex Multiplier provide a complete

Complex Accumulator

文件：137.62 Kbytes Page：8 Pages

Complex Accumulator

文件：137.62 Kbytes Page：8 Pages

Hook and Loop – Ties

文件：150.81 Kbytes Page：2 Pages