20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL

50-125 MHz PECL input/9 CMOS output 3.3 V PLL clock driver

DESCRIPTION The PCK953 is a 3.3 V compatible, PLL-based clock driver device targeted for high performance clock tree designs. With output frequencies of up to 125 MHz, and output skews of 100 ps, the PCK953 is ideal for the most demanding clock tree designs. The devices employ a fully differentia

20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL

20 MHz to 125 MHz PECL input, 9 CMOS output, 3.3 V PLL

封装/外壳：32-LQFP 包装：托盘 描述：IC DRVR CLK PECL 3.3V 32LQFP 集成电路（IC） 时钟发生器，PLL，频率合成器

封装/外壳：32-LQFP 包装：托盘 描述：IC DRVR CLK PECL 3.3V 32LQFP 集成电路（IC） 时钟发生器，PLL，频率合成器

CONN PLUG USB3.0 MICRO USB B SLD

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AC Rated, Radial Leaded Box, UL 810 Fail Safe, Rated 10,000 AFC

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