The MC14076B 4−Bit Register consists of four D−type flip−flops operating synchronously from a common clock. OR gated output−disable inputs force the outputs into a high−impedance state for use in bus organized systems. OR gated data−disable inputs cause the Q outputs to be fed back to the D inputs of the flip−flops. Thus they are inhibited from changing state while the clocking process remains undisturbed. An asynchronous master root is provided to clear all four flip−flops simultaneously independent of the clock or disable inputs.

Features

• Three−State Outputs with Gated Control Lines

• Fully Independent Clock Allows Unrestricted Operation for the Two

Modes: Parallel Load and Do Nothing

• Asynchronous Master Reset

• Four Bus Buffer Registers

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Capable of Driving Two Low−Power TTL Loads or One Low−Power

Schottky TTL Load Over the Rated Temperature Range

• Pb−Free Packages are Available*