The MC100EL39 is a low skew ÷2/4, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned.

Features

• 50 ps Output-to-Output Skew

• Synchronous Enable/Disable

• Master Reset for Synchronization

• ESD Protection: Human Body Model; > 2 kV,

Machine Model; > 100 V

• The 100 Series Contains Temperature Compensation

• PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V

• NECL Mode Operating Range: VCC = 0 V with

VEE = −4.2 V to −5.7 V

• Internal Input Pulldown Resistors on EN, MR, CLK(s), and

DIVSEL(s)

• Q Output will Default LOW with Inputs Open or at VEE

• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

• Moisture Sensitivity Level 1

For Additional Information, see Application Note AND8003/D

• Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index 28 to 34

• Transistor Count = 419 devices

• Pb−Free Packages are Available*