Features and benefits

2.1 RF functionality

• As a highly integrated high performance full NFC Forum-compliant frontend IC for contactless communication

at 13.56 MHz, this NFC frontend IC utilizes an outstanding modulation and demodulation concept completely

integrated for relevant 13.56 MHz based contactless communication methods and protocols.

PN5190B2 supports communication with all products of the MIFARE product-based card family including

MIFARE Ultralight, MIFARE Classic 1K/4K, MIFARE DESFire EV1/EV2 and MIFARE Plus cards CRYPTO

implemented in hardware for R/W of all NXP MIFARE product-based cards (includes intellectual-property

licensing rights for NXP ISO/IEC 14443-A, Innovatron ISO/IEC 14443-B, and NXP MIFARE products).

The PN5190B2 frontend IC supports the following RF operating modes:

2.1.1 ISO/IEC14443-A

• Reader/writer mode supporting ISO/IEC 14443-A R/W up to 848 kbit/s

2.1.2 ISO/IEC14443-B

• Reader/writer mode supporting ISO/IEC 14443-B up to 848 kBit/s

2.1.3 FeliCa

• Reader/writer mode supporting FeliCa 212 kBit/s and 424 kBit/s (without crypto)

2.1.4 Tag type reading

• Supports reading of all NFC tag types (type 1, type 2, type 3, type 4A and type 4B, type 5)

2.1.5 MIFARE card reading

• Reader/writer communication mode for the MIFARE card family including MIFARE Classic

2.1.6 ISO/IEC 15693

• Reader/writer mode supporting ISO/IEC 15693 (ICODE)

• Proprietary data rates based on ISO/IEC15693 with 106 kbit and 212 kbit/s (for NXP NTAG 5 communication)

2.1.7 ISO/IEC 18000-3 Mode 3

• Reader/writer mode supporting ISO/IEC 18000-3 Mode 3

2.1.8 ISO/IEC 18092

• ISO/IEC 18092 (NFC-IP1)

2.1.9 ISO/IEC 21481

• ISO/IEC 21481 (NFC-IP-2)

2.1.10 Peer to peer

• P2P Passive 106 kbit/s TO 424 kbit/s, Initiator and Target

• P2P Active 106 kbit/s TO 424 kbit/s, Initiator and Target

• Proprietary passive communication for type A up to 848 kbit/s

• Functionality according to ISO/IEC 21481 (NFC-IP-2)

2.1.11 Card emulation

• ISO/IEC4443-A card mode from 106 Kbit/s up to 848 Kbit/s (PICC) with active load modulation for increased

communication range.

2.2 Host interface

• One host interface based on SPI is implemented:

– SPI interface with data rates up to 15 Mbit/s with MOSI, MISO, NSS and SCK signals

– Interrupt request line to inform host controller on events

– Independent TX and RX buffer for RF data with size of 1024 bytes each

2.3 Integrated DC-DC

• The PN5190B2 implements an integrated DC-DC which can be used to supply the transmitter. Since the

supply voltage of the transmitter LDO can be up to 6.0 Volts, this simplifies the design of the power supply.

A single supply concept for the RF system, e.g. with single 3.3 V supply, is possible and allows making use of

the maximum RF output power by providing a maximum transmitter supply voltage.

The integrated DC-DC is used by the dynamic power control (DPC) to reduce the maximum power dissipation

of the chip.

The usage of the DC-DC is optional.

For applications making use of the low-power card detection, the DC-DC is available. For applications using

the ultra low-power card detection (ULPCD), the DC-DC cannot be used.

Applications

• Payment

• Physical access

• eGov