Feature

16-Bit CPU (Enhanced S12 Core – CPU12)

— Additional (superset) instructions to improve 32 bit calculations and semaphore handling

— Now possible to access large data segments independent of PPAGE

New XGATE Module

— Programmable, high performance DMA module – up to 80 MIPS RISC performance

— Transfers data to or from all peripherals and RAM without CPU intervention or CPU wait states

— Can perform simple operations on data (logical, shifts, arithmetic, bit operations)

— Enables Full CAN capability when used in conjunction with MXCAN module

— Full LIN master or slave capability when used in conjunction with the six integrated LIN SCI modules

— Can interrupt the HCS12X CPU signalling transfer completion

— Triggers from any hardware module as well as from the CPU possible

• Non-Multiplexed External Bus

— 22 address/16 data wide

— Support for external WAIT input or internal wait cycles to adapt MCU speed to peripheral speed requirements

— Upto three chip select outputs to select 16K, 2M and 4MByte address spaces

— Supports glueless interface to popular asynchronous RAMs and Flash devices

— External address space 4MByte for Data and Program space (144 pin package only)

• System Integration Modules – including Enhanced Interrupt Controller

— CRG (windowed COP watchdog, real time interrupt, clock monitor, clock generation and reset)

— EBI (non-multiplexed external bus interface)

— INT (interrupt control) with 8 levels of nested interrupt, new flexible assignment of interrupt sources to

each interrupt level.

• Five MXCAN Modules with FULL CAN capability when used in conjunction with XGATE

— CAN 2.0 A, B software compatible. Five receive and three transmit buffers

— Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or 8 x 8 bit

— Four separate interrupt channels for Receive, Transmit, Error and Wake-up

— Low-pass filter wake-up function in STOP mode

— Loop-back for self test operation