Features

Central Processing Unit (CPU16) -16-Bit Architecture -Full Set of 16-Bit Instructions -Three 16-Bit Index Registers Two 16-Bit Accumulators - Control-Oriented Digital Signal Processing Capability -1 Megabyte of Program Memory and 1 Megabyte of Data Memory High-Level Language Support - Fast Interrupt Response Time Background Debugging Mode Single-Chip Integration Module (SCIM) - Single-Chip or Expanded Modes of Operation - External Bus Support in Expanded Mode -Nine Programmable Chip Select Outputs -Emulation-Support Chip Select Output - System Protection Logic -Watchdog Timer, Clock Monitor, and Bus Monitor Parallel Ports Option on Address and Data Bus in Single-Chip Mode -Phase-Locked Loop (PLL) Clock System Time Processor Unit (TPU) - Dedicated Microengine Operating Independently of CPU16 -16 Independently Programmable Channels and Pins -Two Timer Count Registers with Programmable Prescalers Selectable Channel Priority Levels • General-Purpose Timer (GPT) -Two 16-Bit Free-Running Counters with Prescaler -Three Input Capture Channels - Four Output Compare Channels - One Input Capture/Output Compare Channel - One Pulse Accumulator/Event Counter Input -Two Pulse-Width Modulation Outputs -Optional External Clock Input 8/10-Bit Analog-to-Digital Converter (ADC) -Eight Channels, Eight Result Registers -Eight Automated Modes - Three Result-Alignment Modes Multichannel Communication Interface (MCCI) -Dual Serial Communication Interface (SCI) - Serial Peripheral Interface (SPI) • TPU Emulation RAM Module (TPURAM) -2 Kbyte Static RAM Array, Mappable to any 2 Kbyte Boundary -TPU Microcode Emulation Standby RAM Module (STBRAM) -2 Kbyte Static RAM Array, Mappable to any 2 Kbyte Boundary - External Standby Voltage Supply Input and Power-Loss Flag • Flash EEPROM Module (FLASH) -48 Kbyte, Bulk-Erasable 16-Bit Array -Boot ROM Capability