General description

The LPC86x is an Arm Cortex-M0+ based, low-cost 32-bit MCU family operating at CPU

frequencies of up to 60 MHz. The LPC86x supports up to 64 KB of flash memory and

8 KB of SRAM.

The peripheral complement of the LPC86x includes a CRC engine, one I2C-bus interface,

one I3C-MIPI bus interface, up to three USARTs, up to two SPI interfaces, one multi-rate

timer, self-wake-up timer, two FlexTimers (one with full motor control feature), a DMA, one

12-bit ADC, one analog comparator, function-configurable I/O ports through a switch

matrix, an input pattern match engine, and up to 54 general-purpose I/O pins.

Features and benefits

 System:

 Arm Cortex-M0+ processor (revision r0p1), running at frequencies of up to 60 MHz

with single-cycle multiplier and fast single-cycle I/O port.

 Arm Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

 System tick timer.

 AHB multilayer matrix.

 Serial Wire Debug (SWD) with four break points and two watch points. JTAG

boundary scan (BSDL) supported only.

 Memory:

 Up to 64 KB on-chip flash programming memory with 64 Byte page write and

erase.

 Code Read Protection (CRP).

 Up to 8 KB SRAM consisting of contiguous SRAM banks.

 Bit-band addressing is supported to permit atomic operations to modify a single bit.

 ROM API support:

 Boot loader.

 Supports Flash In-Application Programming (IAP).

 Supports In-System Programming (ISP) through USART.

 FRO API.

 Digital peripherals:

 High-speed GPIO interface connected to the Arm Cortex-M0+ I/O bus with up to 54

General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,

programmable open-drain mode, input inverter, and digital filter. GPIO direction

control supports independent set/clear/toggle of individual bits. The GPIO pins are

tri-state when power is on.

 High-current source output driver (20 mA) on four pins.

 High-current sink driver (20 mA) on two true open-drain pins.

 GPIO interrupt generation capability with a boolean pattern-matching feature on

eight GPIO inputs.

 Switch matrix for flexible configuration of each I/O pin function.

 CRC engine.

 DMA with 16 channels and 13 trigger inputs.

 Timers:

 Two FlexTimers with DMA support and a selection of hardware triggers. The first

FlexTimer has six channels and includes support for motor control (including Fault

Control). The second FlexTimer has four channels. This timer does not include

Fault Control but includes a Quadrature Decoder interface. Both FlexTimers are

clocked up to 60 MHz.

 Four-channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to

four programmable, fixed rates.

 Self-Wake-up Timer (WKT) clocked from either Free Running Oscillator (FRO), a

low-power, low-frequency internal oscillator, or an external clock input in the

always-on power domain.

 Windowed Watchdog timer (WWDT).

 Analog peripherals:

 One 12-bit ADC with up to 12 input channels with multiple internal and external

trigger inputs and with sample rates of up to 1.9 Msamples/s. The ADC supports

two independent conversion sequences.

 Comparator with five input pins and external or internal reference voltage.

 Serial peripherals:

 Three USART interfaces with pin functions are assigned through the switch matrix,

support receives idle interrupt, and two fractional baud rate generators.

 Two SPI controllers with pin functions are assigned through the switch matrix.

 One I2C-bus interface. I2C supports Fast-mode Plus with a 1 Mbit/s data rate on

two true open-drain pins and listen mode.

 One controller/target I3C-MIPI bus interface. The I3C supports DDR. It is supported

by the general-purpose DMA controller.

 Clock generation:

 Free Running Oscillator (FRO). This oscillator provides selectable 60 MHz, 48

MHz, and 36 MHz outputs that can be used as a system clock. Also, these outputs

can be divided down to 30 MHz, 24 MHz, and 18 MHz for the system clock. The

FRO is trimmed to 1 accuracy over the entire voltage and temperature range of

0 °C to 70 °C.

 External clock input for clock frequencies of up to 25 MHz.

 Crystal oscillator with an operating range of 1 MHz to 25 MHz.

 1 MHz (+3) low-power oscillator (LPOSC) can be used as a clock source for the

watchdog timer.

 PLL allows CPU operation up to the maximum CPU rate without the need for a

high-frequency crystal. May be run from the system oscillator, the external clock

input, or the internal FRO.

 Clock output function with a divider that can reflect all internal clock sources.

 Power control:

 Reduced power modes: sleep mode, deep-sleep mode, power-down mode, and

deep power-down mode.

 Wake up from deep-sleep and power-down modes on activity on USART, SPI, I2C,

and I3C peripherals.

 Timer-controlled self wake up from deep power-down mode.

 Power-On Reset (POR).

 Brownout detect (BOD).

 Unique device serial number for identification.

 Single power supply (1.8 V to 3.6 V).

 Operating temperature range -40 °C to +105 °C.

 Available in LQFP64, HVQFN48, and HVQFN32 packages.

Applications

 Sensor gateways

 Industrial

 Gaming controllers

 8/16-bit applications

 Consumer

 Climate control

 Simple motor control

 Portables and wearables

 Lighting

 Motor control

 Fire and security applications