1. General description

The LPC804 are an ArmCortex-M0+ based, low-cost 32-bit MCU family operating at CPU

frequencies of up to 15 MHz. The LPC804 supports 32 KB of flash memory and 4 KB of

SRAM.

The peripheral complement of the LPC804 includes a CRC engine, two I2C-bus

interfaces, up to two USARTs, one SPI interface, Capacitive Touch Interface (Cap Touch),

one multi-rate timer, self-wake-up timer, one general purpose 32-bit counter/timer, one

12-bit ADC, one 10-bit DAC, one analog comparator, function-configurable I/O ports

through a switch matrix, an input pattern match engine, Programmable Logic Unit (PLU),

and up to 30 general-purpose I/O pins.

Features and benefits

 System:

 Arm Cortex-M0+ processor (revision r0p1), running at frequencies of up to 15 MHz

with single-cycle multiplier and fast single-cycle I/O port.

 Arm Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC).

 System tick timer.

 AHB multilayer matrix.

 Serial Wire Debug (SWD) with four break points and two watch points. JTAG

boundary scan (BSDL) supported.

 Memory:

 Up to 32 KB on-chip EEPROM based flash programming memory.

 Code Read Protection (CRP).

 4 KB SRAM.

 Dual I/O power (LPC804M111JDH24):

 Independent supplies on each package side permitting level-shifting signals from

one off-chip voltage domain to another and/or interfacing directly to off-chip

peripherals operating at different supply levels.

 The switch matrix provides level shifter functionality to allow up to two selected

signals to be routed from user-selected pins in one voltage domain to selected pins

in the alternate domain. This feature can also be used on a single supply device if

voltage level shifting is not required.

 ROM API support:

 Boot loader.

 Supports Flash In-Application Programming (IAP).

 Supports In-System Programming (ISP) through USART.

 On-chip ROM APIs for integer divide.

 Free Running Oscillator (FRO) API.

 Digital peripherals:

 High-speed GPIO interface connected to the Arm Cortex-M0+ I/O bus with up to 30

General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down resistors,

programmable open-drain mode, and input inverter. GPIO direction control

supports independent set/clear/toggle of individual bits.

 High-current source output driver (20 mA) on five pins.

 GPIO interrupt generation capability with boolean pattern-matching feature on eight

GPIO inputs.

 Switch matrix for flexible configuration of each I/O pin function.

 CRC engine.

 Capacitive Touch Interface.

 Programmable Logic Unit (PLU) to create small combinatorial and/or sequential

logic networks including simple state machines.

 Timers:

 One 32-bit general purpose counter/timer, with four match outputs and three

capture inputs. Supports PWM mode, and external count

 Four channel Multi-Rate Timer (MRT) for repetitive interrupt generation at up to

four programmable, fixed rates.

 Self-Wake-up Timer (WKT) clocked from either Free Running Oscillator (FRO), a

low-power, low-frequency internal oscillator, or an external clock input.

 Windowed Watchdog timer (WWDT).

 Analog peripherals:

 One 12-bit ADC with up to 12 input channels with multiple internal and external

trigger inputs and with sample rates of up to 480 Ksamples/s. The ADC supports

two independent conversion sequences.

 Comparator with five input pins and external or internal reference voltage.

 One 10-bit DAC.

 Serial peripherals:

 Two USART interfaces with pin functions assigned through the switch matrix and

one fractional baud rate generators.

 One SPI controllers with pin functions assigned through the switch matrix.

 Two I2C-bus interface. It supports data rates up to 400 kbit/s on standard digital

pins.

 Clock generation:

 Free Running Oscillator (FRO). This oscillator provides a selectable

9 MHz, 12 MHz and 15 MHz outputs that can be used as a system clock. The FRO

is trimmed to ±1 accuracy over the entire voltage and temperature range of 0 C

to 70 C.

 1 MHz low power oscillator can be used as a clock source.

 Clock output function with divider that can reflect all internal clock sources.

 Power control:

 Reduced power modes: sleep mode, deep-sleep mode, power-down mode, and

deep power-down mode.

 Wake-up from deep-sleep and power-down modes on activity on USART, SPI, and

I2C peripherals.

 Wake-up from deep power-down mode on multiple pins.

 Timer-controlled self wake-up from sleep, deep-sleep, and power-down modes.

 Power-On Reset (POR).

 Brownout detect (BOD).

 Unique device serial number for identification.

 Single power supply (1.71 V to 3.6 V).

 Operating temperature range -40 °C to +105 °C.

 Available in WLCSP20, TSSOP20, TSSOP24, and HVQFN33 packages.

3. Applications

 Sensor gateways

 Industrial

 Gaming controllers

 8/16-bit applications

 Consumer

 Climate control

 Simple motor control

 Portables and wearables

 Lighting

 Motor control

 Fire and security applications