General description

The LPC43S50/S30/S20 are ARM Cortex-M4 based microcontrollers for embedded

applications which include an ARM Cortex-M0 coprocessor, up to 264 kB of SRAM,

security features with AES engine, advanced configurable peripherals such as the State

Configurable Timer/PWM (SCTimer/PWM) and the Serial General-Purpose I/O (SGPIO)

interface, two High-speed USB controllers, Ethernet, LCD, an external memory controller,

and multiple digital and analog peripherals. The LPC43S50/S30/S20 operate at CPU

frequencies of up to 204 MHz.

The ARM Cortex-M4 is a 32-bit core that offers system enhancements such as low power

consumption, enhanced debug features, and a high level of support block integration. The

ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture with

separate local instruction and data buses as well as a third bus for peripherals, and

includes an internal prefetch unit that supports speculative branching. The ARM

Cortex-M4 supports single-cycle digital signal processing and SIMD instructions. A

hardware floating-point unit is integrated in the core.

The ARM Cortex-M0 coprocessor is an energy-efficient and easy-to-use 32-bit core which

is code- and tool-compatible with the Cortex-M4 core. The Cortex-M0 coprocessor offers

up to 204 MHz performance with a simple instruction set and reduced code size. In

LPC43Sx0, the Cortex-M0 coprocessor hardware multiply is implemented as a 32-cycle

iterative multiplier.

Features and benefits

 Cortex-M4 Processor core

 ARM Cortex-M4 processor, running at frequencies of up to 204 MHz.

 Built-in Memory Protection Unit (MPU) supporting eight regions.

 Built-in Nested Vectored Interrupt Controller (NVIC).

 Hardware floating-point unit.

 Non-maskable Interrupt (NMI) input.

 JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch points.

 Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support.

 System tick timer.

 Cortex-M0 Processor core

 ARM Cortex-M0 coprocessor capable of off-loading the main ARM Cortex-M4

application processor.

 Running at frequencies of up to 204 MHz.

 JTAG

 Built-in NVIC.

 On-chip memory

 Up to 264 kB SRAM for code and data use.

 Multiple SRAM blocks with separate bus access. Two SRAM blocks can be

powered down individually.

 64 kB ROM containing boot code and on-chip software drivers.

 64 bit general-purpose OTP memory.

 Two banks (256 bit total) One-Time Programmable (OTP) memory for AES key

storage One bank can store an encrypted key for decoding the boot image.

 AES engine for encryption and decryption of the boot image and data with DMA

support and programmable via a ROM-based API.

 Clock generation unit

 Crystal oscillator with an operating range of 1 MHz to 25 MHz.

 12 MHz Internal RC (IRC) oscillator trimmed to 1.5 accuracy over temperature

and voltage.

 Ultra-low power Real-Time Clock (RTC) crystal oscillator.

 Three PLLs allow CPU operation up to the maximum CPU rate without the need for

a high-frequency crystal. The second PLL is dedicated to the High-speed USB, the

third PLL can be used as audio PLL.

 Clock output.

 Configurable digital peripherals

 Serial GPIO (SGPIO) interface.

 State Configurable Timer (SCTimer/PWM) subsystem on AHB.

 Global Input Multiplexer Array (GIMA) allows to cross-connect multiple inputs and

outputs to event driven peripherals like the timers, SCTimer/PWM, and ADC0/1.

 Serial interfaces

 Quad SPI Flash Interface (SPIFI) with 1-, 2-, or 4-bit data at rates of up to

52 MB per second.

 10/100T Ethernet MAC with RMII and MII interfaces and DMA support for high

throughput at low CPU load. Support for IEEE 1588 time stamping/advanced time

stamping (IEEE 1588-2008 v2).

 One High-speed USB 2.0 Host/Device/OTG interface with DMA support and

on-chip high-speed PHY (USB0).

 One High-speed USB 2.0 Host/Device interface with DMA support, on-chip

full-speed PHY and ULPI interface to external high-speed PHY (USB1).

 USB interface electrical test software included in ROM USB stack.

 Four 550 UARTs with DMA support: one UART with full modem interface; one

UART with IrDA interface; three USARTs support UART synchronous mode and a

smart card interface conforming to ISO7816 specification.

 Up to two C_CAN 2.0B controllers with one channel each. Use of C_CAN controller

excludes operation of all other peripherals connected to the same bus bridge See

 Two SSP controllers with FIFO and multi-protocol support. Both SSPs with DMA

support.

 One SPI controller.

 One Fast-mode Plus I2C-bus interface with monitor mode and with open-drain I/O

pins conforming to the full I2C-bus specification. Supports data rates of up to

1 Mbit/s.

 One standard I2C-bus interface with monitor mode and with standard I/O pins.

 Two I2S interfaces, each with DMA support and with one input and one output.

 Digital peripherals

 External Memory Controller (EMC) supporting external SRAM, ROM, NOR flash,

and SDRAM devices.

 LCD controller with DMA support and a programmable display resolution of up to

1024 H  768 V. Supports monochrome and color STN panels and TFT color

panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel

mapping.

 Secure Digital Input Output (SD/MMC) card interface.

 Eight-channel General-Purpose DMA controller can access all memories on the

AHB and all DMA-capable AHB slaves.

 Up to 164 General-Purpose Input/Output (GPIO) pins with configurable

pull-up/pull-down resistors.

 GPIO registers are located on the AHB for fast access. GPIO ports have DMA

support.

 Up to eight GPIO pins can be selected from all GPIO pins as edge and level

sensitive interrupt sources.

 Two GPIO group interrupt modules enable an interrupt based on a programmable

pattern of input states of a group of GPIO pins.

 Four general-purpose timer/counters with capture and match capabilities.

 One motor control Pulse Width Modulator (PWM) for three-phase motor control.

 One Quadrature Encoder Interface (QEI).

 Repetitive Interrupt timer (RI timer).

 Windowed watchdog timer (WWDT).

 Ultra-low power Real-Time Clock (RTC) on separate power domain with 256 bytes

of battery powered backup registers.

 Alarm timer; can be battery powered.

 Analog peripherals

 One 10-bit DAC with DMA support and a data conversion rate of 400 kSamples/s.

 Two 10-bit ADCs with DMA support and a data conversion rate of 400 kSamples/s.

Up to eight input channels per ADC.

 Unique ID for each device.

 Power

 Single 3.3 V (2.2 V to 3.6 V) power supply with on-chip internal voltage regulator for

the core supply and the RTC power domain.

 RTC power domain can be powered separately by a 3 V battery supply.

 Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep power-down.

 Processor wake-up from Sleep mode via wake-up interrupts from various peripherals.

 Wake-up from Deep-sleep, Power-down, and Deep power-down modes via

external interrupts and interrupts generated by battery powered blocks in the RTC

power domain.

 Brownout detect with four separate thresholds for interrupt and forced reset.

 Power-On Reset (POR).

 Available as LBGA256, TFBGA180, and TFBGA100 packages and as LQFP144 package.

Applications

 Communication hubs

 Automotive aftermarket

 Power management

 Consumer health devices

 Embedded audio applications

 Industrial control

 Industrial automation

 white goods