General description

The LPC3220/30/40/50 embedded microcontrollers were designed for low power, high

performance applications. NXP achieved their performance goals using a 90 nanometer

process to implement an ARM926EJ-S CPU core with a vector floating point co-processor

and a large set of standard peripherals including USB On-The-Go. The

LPC3220/30/40/50 operates at CPU frequencies of up to 266 MHz.

The NXP implementation uses a ARM926EJ-S CPU core with a Harvard architecture,

5-stage pipeline, and an integral Memory Management Unit (MMU). The MMU provides

the virtual memory capabilities needed to support the multi-programming demands of

modern operating systems. The ARM926EJ-S also has a hardware based set of DSP

instruction extensions, which includes single cycle MAC operations, and hardware based

native Jazelle Java Byte-code execution. The NXP implementation has a 32 kB

instruction cache and a 32 kB data cache.

For low power consumption, the LPC3220/30/40/50 takes advantage of NXP’s advanced

technology development to optimize intrinsic power and uses software controlled

architectural enhancements to optimize application based power management.

The LPC3220/30/40/50 also includes 256 kB of on-chip static RAM, a NAND flash

interface, an Ethernet MAC, an LCD controller that supports STN and TFT panels, and an

external bus interface that supports SDR and DDR SDRAM as well as static devices. In

addition, the LPC3220/30/40/50 includes a USB 2.0 full-speed interface, seven UARTs,

two I2C-bus interfaces, two SPI/SSP ports, two I2S-bus interfaces, two single output

PWMs, a motor control PWM, six general purpose timers with capture inputs and compare

outputs, a Secure Digital (SD) interface, and a 10-bit Analog-to-Digital Converter (ADC)

with a touch screen sense option.

For additional documentation, see Section 15 “References”.

Features and benefits

 ARM926EJ-S processor, running at CPU clock speeds up to 266 MHz.

 Vector Floating Point (VFP) coprocessor.

 32 kB instruction cache and 32 kB data cache.

 Up to 256 kB of Internal SRAM (IRAM).

 Selectable boot-up from various external devices: NAND flash, SPI memory, USB,

UART, or static memory.