Features

• Low Cost

• HC05 Core

• 28-Pin SOIC, PDIP, or Windowed DIP Package

• 4672 Bytes of User EPROM (Including 48 Bytes of Page Zero

EPROM and 16 Bytes of User Vectors)

• 239 Bytes of Bootloader ROM

• 176 Bytes of On-Chip RAM

• 4-Channel 8-Bit A/D Converter

• SIOP Serial Communications Port

• 16-Bit Timer with Output Compare and Input Capture

• 20 Bidirectional I/O Lines and 1 Input-Only line

• PC0 and PC1 High-Current Outputs

• Single-Chip, Bootloader, and Test Modes

• Power-Saving Stop, Halt, and Wait Modes

• Static EPROM Mask Option Register (MOR) Selectable Options:

– COP Watchdog Timer Enable or Disable

– Edge-Sensitive or Edge- and Level-Sensitive External

Interrupt

– SIOP Most Significant Bit (MSB) or Least Significant Bit (LSB)

First

– SIOP Clock Rates: OSC Divided by 8, 16, 32, or 64

– Stop Instruction Mode, STOP or HALT

– EPROM Security External Lockout

– Programmable Keyscan (Pullups/Interrupts) on PA0–PA7