Features

Features of the MC68HC08KL8 include:

• High-Performance M68HC08 Architecture

• Fully Upward-Compatible Object Code with M6805, M146805,

and M68HC05 Families

• 1.5-MHz Internal Bus Operation

• Eight Kbytes of On-Chip Read-Only Memory (ROM)

• On-Chip Programming Firmware for Use with Host Personal

Computer

• ROM Data Security1

• 368 Bytes of On-Chip Random Access Memory (RAM)

• 39 General-Purpose Input/Output (I/O) Ports, 24 with Software

Configurable Pullups

• 16-Bit, 2-Channel Timer Interface Module (TIM)

• 8-Bit Keyboard Interrupt (KBI) Port

• Available in a 52-lead plastic quad flat pack (QFP) package:

– 39 general-purpose input/output (I/O), 24 with software

configurable pullups

– 16-bit, 2-channel timer interface module (TIM)

– Eight light-emitting diode (LED) direct drive port pins

• Available in a 42-lead shrink dual in-line plastic (SDIP) package:

– 29 general-purpose input/output (I/O), 21 with software

configurable pullups

– Five light-emitting diode (LED) direct drive port pins

• Full Compatibility with Universal Serial Bus (USB) Specification

Rev. 1.0

– Supports Non-Isochronous Data

– Bidirectional Half-Duplex Link

– 1.5 Mbps Data Rate (Low Speed)

• On-Chip USB Transceiver

• On-Chip 3.3-V Regulator for USB Transceiver

• USB Data Control Logic

– Packet Decoding/Generation

– CRC Generation and Checking

– Non-Return-to-Zero Inverted (NRZI) Encoding/Decoding

and Bit-Stuffing

• Two 8-Byte Transmit Buffers

– One Dedicated for Endpoint 0

– One Shared by Endpoint 1 and Endpoint 2

• One 8-Byte Receive Buffer

– Dedicated for Control Endpoint 0

• USB Suspend/Resume Operation

• System Protection Features

– Optional Computer Operating Properly (COP) Reset

– Illegal Opcode Detection with Optional Reset

– Illegal Address Detection with Optional Reset

• Low-Power Design, Fully Static with Stop Mode and Wait Mode

• Master Reset Pin with Internal Pullup and Power-On Reset

• External Asynchronous Interrupt Pin with Internal Pullup (IRQ1)