GENERAL DESCRIPTION

The NuMicro® M0A21/M0A23 series is a 32-bit microcontroller based on Arm® Cortex®-M0 core. It provides compact package with highly flexible digital pin function assignment, rich analog peripherals, -40°C to 125°C operating temperature, 2.4V ~ 5.5V operating voltage, CAN 2.0B and LIN interface for robust communication. The NuMicro® M0A21/M0A23 series targets robust and high operating temperature applications, such as 24 GHz mmWave radar, Battery Management System (BMS), car lighting, electric window lifter, and power seat.

The NuMicro® M0A21/M0A23 series provide SSOP20 and TSSOP28 package with rich analog and digital functions, which are especially suitable for small form factor applications. SSOP20 provides up to 18 IO pins and TSSOP28 provides up to 26 IO pins. Each IO pin of the M0A21/M0A23 series can be arbitrarily assigned to digital peripherals, such as UART, SPI, and PWM. The M0A21/M0A23 series provides rich analog functions including 17-ch 12-bit 500 KSPS ADC, 1 set of 5-bit DAC and 2 sets of ACMP in both SSOP20 and TSSOP28 package. Moreover, it provides low voltage reset (LVR) and brown-out detector (BOD) to ensure the system safety.

The NuMicro® M0A21/M0A23 series runs up to 48 MHz and supports hardware divider. It provides 32 Kbytes Flash memory, 4 Kbytes SRAM and 2 Kbytes LDROM for ISP (In-System Programming) feature for easily firmware update. It is equipped with plenty of peripherals including up to four 32-bit timers, 6-ch 16-bit PWM generators, 1 set of CAN 2.0B controller, 2 sets of LIN functions, 5-ch PDMA, 2 sets of UART with One-Wire mode, IrDA and RS485 functions. Besides, the M0A21/M0A23 series provides two sets of Universal Serial Control Interfaces (USCI) that can be configured as UART, SPI or I2C.

The package types of the M0A21/M0A23 series are included SSOP20 (5.3x7.2x1.75 mm) and TSSOP28 (4.4x9.7x1.0 mm).

FEATURES

Core and System

Arm® Cortex®-M0

 Arm® Cortex®-M0 core, running up to 48 MHz

 Built-in Nested Vectored Interrupt Controller (NVIC)

 24-bit system tick timer

 Programmble and maskable interrupt

 Low Power Sleep mode by WFI and WFE instructions

Brown-out Detector (BOD)

 Four-level BOD with brown-out interrupt and reset option. (4.4V/3.7V/2.7V/2.3V)

Low Voltage Reset (LVR)

 LVR with 2.22V threshold voltage level

Security

 96-bit Unique ID (UID).

 128-bit Unique Customer ID (UCID).

 One built-in temperature sensor.

32-bit H/W Divider(HDIV)

 Signed (two’s complement) integer calculation

 32-bit dividend with 16-bit divisor calculation capacity

 32-bit quotient and 32-bit remainder outputs (16-bit remainder with sign extends to 32-bit)

 6 HCLK clocks taken for one cycle calculation Memories

Boot Loader

 Nuvoton ISP (In-System-Programming) tool for firmware upgrade via UART

 ISP/IAP libraries

Flash

 Up to 32 KB application ROM (APROM)

 2 KB on-chip Flash for user-defined loader (LDROM)

 All on-chip Flash support 512 bytes page erase

 Fast Flash programming verification with CRC

 On-chip Flash programming with In-Chip Programming (ICP), In-System Programming (ISP) and In-Application Programming (IAP) capabilities

 Configurable boot up sources including boot loader, user-defined loader (LDROM) or Application ROM (APROM)

 Data Flash with configurable memory size

 2-wired ICP Flash updating through SWD interface

 32-bit and multi-word Flash programming function

SRAM

 Up to 4 KB embedded SRAM

 Supports byte-, half-word- and word-access

 Supports PDMA mode

Cyclic Redundancy Calculation (CRC)

 Supports CRC-CCITT, CRC-8, CRC-16 and CRC-32 polynomials

 Programmable initial value

 Programmable order reverse setting and one’s complement setting for input data and CRC checksum

 8-bit, 16-bit, and 32-bit data width

 8-bit write mode with 1-AHB clock cycle operation

 16-bit write mode with 2-AHB clock cycle operation

 32-bit write mode with 4-AHB clock cycle operation

 Uses DMA to write data with performing CRC operation

Peripheral DMA (PDMA)

 Supports up to 5 independent configurable channels for automatic data transfer between memories and peripherals

 Basic and Scatter-Gather transfer modes

 Each channel supports circular buffer management using Scatter-Gather Transfer mode

 Stride function for rectangle image data movement

 Fixed-priority and Round-robin priorities modes

 Single and burst transfer types

 Byte-, half-word- and word tranfer unit with count up to 65536

 Request source can be from software, UART, ADC, PWM and Timer

Clocks

External Clock Source

 4~24 MHz High-speed eXternal crystal oscillator (HXT) for precise timing operation

 32.768 kHz Low-speed eXternal crystal oscillator (LXT) for low-power system operation

 Supports clock failure detection for external crystal oscillators and exception generatation (NMI)

Internal Clock Source

 48 MHz High-speed Internal RC oscillator (HIRC) trimmed to

±0.25 accuracy that can optionally be used as a system clock

 38.4 kHz Low-speed Internal RC oscillator (LIRC) for watchdog timer and wakeup operation

Timers

32-bit Timer

 Four sets of 32-bit timers with 24-bit up counter and one 8-bit pre-scale counter from independent clock source

 One-shot, Periodic, Toggle and Continuous Counting operation modes

 Supports event counting function to count the event from external pins

 Supports external capture pin for enhanced interval measurement and resetting 24-bit up counter

 Supports chip wake-up from Idle/Power-down mode if a timer interrupt signal is generated

 Timer interrupt flag or external capture interrupt flag to trigger PWM, ADC and PDMA.

PWM

 Three 16-bit counters with 12-bit prescale for six 48 MHz PWM output channels.

 Supports independent mode for PWM output/Capture input channel

 Supports complementary mode for 3 complementary paired PWM output channel

 Dead-time insertion with 12-bit resolution

 Two compared values during one period

 Supports 16-bit resolution PWM counter

 Up, down or up-down PWM counter type

 Supports mask function and tri-state enable for each PWM pin

 Supports brake function

 Up to 6 independent input capture channels with 16-bit resolution counter

 Counter synchronous start function

 Able to trigger ADC to start conversion.

Watchdog

 20-bit free running up counter for WDT time-out interval.

 Selectable time-out interval (24 ~ 220) and the time-out interval is 416us ~ 27.3 s if WDT_CLK = 38.4 kHz (LIRC).

 System kept in reset state for a period of (1 / WDT_CLK) * 63.

 Able to wake up from Power-down or Idle mode

 Interrupt or reset selectable on watchdog time-out

 Supports selectable WDT reset delay period, including 1026, 130, 18 or 3 WDT_CLK reset delay period.

 Supports to force WDT enabled after chip powered on or reset by setting CWDTEN[2:0] in Config0 register.

 Supports WDT time-out wake-up function only if WDT clock source is selected as LIRC or LXT.

Window Watchdog

 Clock sources from HCLK/2048 (default selection) or LIRC

 Window set by 6-bit down counter with 11-bit prescale

 WWDT counter suspends in Idle/Power-down mode

 Supports Interrupt

Analog Interfaces

Analog-to-Digital Converter (ADC)

 Analog input voltage range: 0 ~ AVDD (voltage of VDD pin).

 12-bit resolution and 10-bit accuracy is guaranteed.

 Up to 17 single-end analog input channels or 8 differential analog input channels

 Maximum ADC peripheral clock frequency is 16 MHz.

 Up to 500 KSPS sampling rate.

 Four operation modes:

- Single mode: A/D conversion is performed one time on a specified channel.

- Burst mode: A/D converter samples and converts the specified single channel and sequentially stores the result in FIFO.

- Single-cycle Scan mode: A/D conversion is performed only one cycle on all specified channels with the sequence from the smallest numbered channel to the largest numbered channel.

- Continuous Scan mode: A/D converter continuously performs Single-cycle Scan mode until software stops A/D conversion.

 An A/D conversion can be started by:

 Software Write 1 to ADST bit.

 External pin (STADC).

 Timer 0~3 overflow pulse trigger.

 PWM trigger.

 Each conversion result is held in data register of each channel with valid and overrun indicators.

 Conversion result can be compared with specified value and user can select whether to generate an interrupt when conversion result matches the compare register setting.

 4 internal channels band-gap voltage (VBG), temperature sensor (VTEMP), internal reference voltage and DAC0 output

 Supports PDMA transfer mode

Digital to Analog Converter (DAC)

 Supports one 5-bit 100 KSPS voltage type DAC

 Analog output voltage range: 0~AVDD (voltage of VDD pin)

 Reference voltage from internal reference voltage VREF pin or AVDD

 DAC maximum conversion updating rate 100K sps

 Rail to rail settle time 10us

 Supports software and timer0~3 trigger to start DAC conversion

 Supports PDMA mode

Analog Comparator (ACMP)

 Analog input voltage range: 0 ~ AVDD (voltage of VDD pin)

 Up to two rail-to-rail analog comparators

 Supports hysteresis function

 Supports wake-up function

 Selectable input sources of positive input and negative input

ACMP0 supports:

 3 multiplexed I/O pins at positive sources:

- ACMP0_P0, Comparator Reference Voltage (CRV), and DAC0 output

 5 negative sources:

- ACMP0_N0, ACMP0_N1, ACMP0_N2, ACMP0_N3

- Comparator Reference Voltage (CRV)

ACMP1 supports:

 3 multiplexed I/O pins at positive sources:

- ACMP1_P0, Comparator Reference Voltage (CRV), and DAC0 output

 5 negative sources:

ACMP1_N

 ACMP1_N0, ACMP1_N1, ACMP1_N2, ACMP1_N3

 Comparator Reference Voltage (CRV)

 Shares one ACMP interrupt vector for all comparators

 Interrupts generated when compare results change (Interrupt event condition is programmable)

 Supports triggers for break events and cycle-by-cycle control for PWM

 Supports window compare mode and window latch mode

Communication Interfaces

UART

 Supports up to 2 UARTs: UART0, UART1

 UART baud rate clock from LXT (32.768 kHz) with 9600bps can work normally in power down mode even system clock is stopped

 Full-duplex asynchronous communications

 Separates receive and transmit 16/16 bytes entry FIFO for data payloads

 Supports hardware auto-flow control (RX, TX, CTS and RTS) and programmable receiver buffer trigger level

 Supports programmable baud rate generator for each channel individually

 Supports 8-bit receiver buffer time-out detection function

 Programmable transmitting data delay time between the last stop and the next start bit

by setting DLY (UART_TOUT [15:8])

 Supports Auto-Baud Rate measurement and baud rate compensation function

 Supports break error, frame error, parity error and receive/transmit buffer overflow detection function

 Fully programmable serial-interface characteristics

 Programmable number of data bit, 5-, 6-, 7-, 8- bit character

 Programmable parity bit, even, odd, no parity or stick parity bit generation and detection

 Programmable stop bit, 1, 1.5, or 2 stop bit generation

 Supports LIN function mode

 Supports LIN master/slave mode

 Supports programmable break generation function for transmitter

 Supports break detection function for receiver

 Supports LIN slave header time-out detection function

 Supports LIN response time-out detection function

 Supports LIN wake-up function

 Supports IrDA SIR function mode

 Supports for 3/16 bit duration for normal mode

 Supports RS-485 mode

 Supports RS-485 9-bit mode

 Supports hardware or software enables to program nRTS pin to control RS-485 transmission direction

 Supports nCTS, incoming data, Received Data FIFO reached threshold and RS-485 Address Match (AAD mode) wake-up function

 Supports PDMA mode

 Supports Single-wire function mode.

CAN

 Supports CAN protocol version 2.0 part A and B

 Bit rates up to 1 MBit/s

 32 Message Objects

 Supports wake-up function

Universal Serial Control Interface (USCI)

 Supports one set of USCI

 USCI supports UART, SPI and I2C function

 Single byte TX and RX buffer mode

UART

 One transmit buffer and two receive buffer for data payload

 Hardware auto flow control function and programmable flow control trigger level

 Programmable baud-rate generator

 Supports 9-Bit Data Transfer

 Baud rate detection by built-in capture event of baud rate generator

 Supports Wake-up function (Data and nCTS Wakeup Only)

 Supports PDMA transfer SPI

 Master or Slave mode operation (maximum frequency: master = fPCLK / 2, slave < fPCLK / 5)

 Configurable bit length of a transfer word from 4 to 16-bit

 One transmit buffer and two receive buffer for data payload

 MSB first or LSB first transfer sequence

 Word suspend function

 Supports PDMA transfer

 Supports 3-wire, no slave select signal, bi-direction interface

 Wake-up function: input slave select transition

 Supports one data channel half-duplex transfer

I2C

 Full master and slave device capability

 7-bit addressing mode (10-bit mode Not supported)

 Communication in standard mode (100 kbps) or in fast mode (up to 400 kbps)

 Multi-master bus

 One transmit buffer and two receive buffer for data payload

 Supports 10-bit bus time-out capability

 Supports Bus monitor mode

 Power down wake-up by data toggle or address match

 Multiple address recognition

 Device address flag

 Setup/hold time programmable

GPIO

 Four I/O modes:

- Quasi-bidirectional mode

- Push-Pull Output mode

- Open-Drain Output mode

- Input only with high impendence mode

 Schmitt trigger input

 I/O pin configured as interrupt source with edge/level trigger setting

 Supports high drive and high sink current I/O

 Supports independent pull-up control

 Maximum I/O Speed is 24 MHz when VDD = 2.4 ~ 5.5V.

 Supports up to 18/26 GPIOs for SSOP20 TSSOP28 respectively

 Enabling the pin interrupt function will also enable the wake-up function