1. General description

The HEF4027B is a dual positive-edge triggered JK flip-flop featuring independent set direct (nSD),

clear direct (nCD), clock inputs (nCP) and complementary outputs (nQ and nQ). Data is accepted

when nCP is LOW, and transferred to the output on the positive-going edge of the clock. The

asynchronous clear-direct (nCD) and set-direct (nSD) are independent and override the nJ, nK,

and nCP inputs. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower

clock rise and fall times. Inputs include clamp diodes. This enables the use of current limiting

resistors to interface inputs to voltages in excess of VDD.

2. Features and benefits

• Wide supply voltage range from 3.0 V to 15.0 V

• CMOS low power dissipation

• High noise immunity

• Fully static operation

• 5 V, 10 V, and 15 V parametric ratings

• Standardized symmetrical output characteristics

• Complies with JEDEC standard JESD 13-B

• ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-B exceeds 200 V

• Specified from -40 °C to +85 °C

3. Applications

• Registers

• Counters

• Control circuits