1. General description

The 74LVT640 is an 8-bit inverting transceiver with 3-state outputs. The device features an output

enable (OE) and send/receive (DIR) for direction control. A HIGH on OE causes the outputs to

assume a high-impedance OFF-state. Bus hold data inputs eliminate the need for external pull-up

resistors to define unused inputs

2. Features and benefits

• 3-state buffers

• Wide supply voltage range from 2.7 to 3.6 V

• Overvoltage tolerant inputs to 5.5 V

• BiCMOS high speed and output drive

• Direct interface with TTL levels

• IOFF circuitry provides partial Power-down mode operation

• Octal bidirectional bus interface

• Input and output interface capability to systems at 5 V supply

• Output capability: +64 mA and -32 mA

• Bus-hold data inputs eliminate the need for external pull-up resistors for unused inputs

• Live insertion/extraction permitted

• Power-up 3-state

• No bus current loading when output is tied to 5 V bus

• Latch-up performance exceeds 500 mA per JESD 78 Class II Level B

• Complies with JEDEC standards

• JESD8C (2.7 V to 3.6 V)

• ESD protection:

• MIL STD 883 method 3015: exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V

• Specified from -40 °C to +85 °C