1. General description

The 74LV164 is an 8-bit serial-in/parallel-out shift register. The device features two serial data

inputs (DSA and DSB), eight parallel outputs (Q0 to Q7). Data is entered serially through DSA or

DSB and either input can be used as an active HIGH enable for data entry through the other input.

Data is shifted on the LOW-to-HIGH transition of the clock input (CP). A LOW on the master reset

input (MR) clears the register and forces all outputs LOW, independently of other inputs.

Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to

voltages in excess VCC.

2. Features and benefits

• Wide supply voltage range from 1.0 V to 5.5 V

• CMOS low power dissipation

• Optimized for low-voltage applications: 1.0 V to 3.6 V

• Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V

• Typical VOLP (output ground bounce): < 0.8 V at VCC = 3.3 V and Tamb = 25 °C

• Typical VOHV (output VOH undershoot): > 2 V at VCC = 3.3 V and Tamb = 25 °C

• Gated serial data inputs

• Asynchronous master reset

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B

• Complies with JEDEC standards:

• JESD8-7 (1.65 V to 1.95 V)

• JESD8-5 (2.3 V to 2.7 V)

• JESD8C (2.7 V to 3.6 V)

• JESD36 (4.5 V to 5.5 V)

• ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V

• Specified from -40 °C to +80 °C and from -40 °C to +125 °C.