1. General description

The 74AXP1T45 is a single bit, dual supply transceiver with 3-state output that enables

bidirectional level translation. It features two 1-bit input-output ports (A and B), a direction control

input (DIR) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at any

voltage between 0.9 V and 5.5 V making the device suitable for translating between any of the low

voltage nodes (0.9 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). No power supply sequencing is

required and output glitches during power supply transitions are prevented using patented circuitry.

As a result glitches will not appear on the outputs for supply transitions during power-up/down

between 20 mV/μs and 5.5 V/s. Pins A and DIR are referenced to VCC(A) and pin B is referenced

to VCC(B). A HIGH on DIR allows transmission from A to B and a LOW on DIR allows transmission

from B to A.

The device is fully specified for partial power-down applications using IOFF. The IOFF circuitry

disables the output, preventing any damaging backflow current through the device when it is

powered down. In suspend mode when either VCC(A) or VCC(B) are at GND level, both A and B are

in the high-impedance OFF-state.

2. Features and benefits

• Wide supply voltage range:

• VCC(A): 0.9 V to 5.5 V

• VCC(B): 0.9 V to 5.5 V

• Low input capacitance; CI = 1.5 pF (typical)

• Low output capacitance; CO = 3.8 pF (typical)

• Low dynamic power consumption; CPD = 11 pF (typical)

• Low static power consumption; ICC = 2 μA (25 °C maximum)

• High noise immunity

• Complies with JEDEC standard:

• JESD8-12 (1.1 V to 1.3 V; inputs)

• JESD8-11 (1.4 V to 1.6 V)

• JESD8-7 (1.65 V to 1.95 V)

• JESD8-5 (2.3 V to 2.7 V)

• JESD8C (2.7 V to 3.6 V)

• JESD12-6 (4.5 V to 5.5 V)

• ESD protection:

• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V

• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V

• Latch-up performance exceeds 100 mA per JESD78D Class II

• Inputs accept voltages up to 5.5 V

• Low noise overshoot and undershoot < 10 of VCCO

• IOFF circuitry provides partial power-down mode operation

• Specified from -40 °C to +125 °C