位置:74ALVCH16646DGG > 74ALVCH16646DGG详情

74ALVCH16646DGG中文资料

厂家型号

74ALVCH16646DGG

文件大小

250.76Kbytes

页面数量

17

功能描述

16-bit bus transceiver/register; 3-state

总线收发器 18BIT UNIV. BUS

数据手册

原厂下载下载地址一下载地址二到原厂下载

生产厂商

NEXPERIA

74ALVCH16646DGG数据手册规格书PDF详情

1. General description

The 74ALVCH16646 consists of 16 non-inverting bus transceiver circuits with 3-state outputs,

D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from

the internal registers. Data on the ‘A’ or ‘B’ bus will be clocked in the internal registers, as the

appropriate clock (nCPAB or nCPBA) goes to a HIGH logic level. Output enable (nOE) and

direction (nDIR) inputs are provided to control the transceiver function. In the transceiver mode,

data present at the high-impedance port may be stored in either the ‘A’ or ‘B’ register, or in both.

The select source inputs (nSAB and nSBA) can multiplex stored and real-time (transparent mode)

data. The direction (nDIR) input determines which bus will receive data when nOE is active (LOW).

In the isolation mode (nOE = HIGH), ‘A’ data may be stored in the ‘B’ register and/or ‘B’ data may

be stored in the ‘A’ register.

When an output function is disabled, the input function is still enabled and may be used to store

and transmit data. Only one of the two buses, ‘A’ or ‘B’ may be driven at a time.

To ensure the high impedance state during power up or power down, nOE should be tied to VCC

through a pullup resistor; the minimum value of the resistor is determined by the current-sinking/

current-sourcing capability of the driver.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

2. Features and benefits

• Wide supply voltage range of 2.3 V to 3.6 V

• CMOS low power consumption

• Direct interface with TTL levels

• Current drive ±24 mA at VCC = 3.0 V.

• MULTIBYTE flow-through standard pin-out architecture

• Low inductance multiple VCC and GND pins for minimize noise and ground bounce

• All data inputs have bushold

• Output drive capability 50 Ω transmission lines at 85 °C

• Complies with JEDEC standards:

• JESD8-5 (2.3 V to 2.7 V)

• JESD8B/JESD36 (2.7 V to 3.6 V)

• ESD protection:

• HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

• CDM JESD22-C101E exceeds 1000 V

74ALVCH16646DGG产品属性

  • 类型

    描述

  • 型号

    74ALVCH16646DGG

  • 功能描述

    总线收发器 18BIT UNIV. BUS

  • RoHS

  • 制造商

    Fairchild Semiconductor

  • 逻辑类型

    CMOS

  • 逻辑系列

    74VCX

  • 每芯片的通道数量

    16

  • 输入电平

    CMOS

  • 输出电平

    CMOS

  • 输出类型

    3-State

  • 高电平输出电流

    - 24 mA

  • 低电平输出电流

    24 mA

  • 传播延迟时间

    6.2 ns

  • 电源电压-最大

    2.7 V, 3.6 V

  • 电源电压-最小

    1.65 V, 2.3 V

  • 最大工作温度

    + 85 C

  • 封装/箱体

    TSSOP-48

  • 封装

    Reel

更新时间:2026-2-20 22:59:00
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PHI
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原装现货海量库存欢迎咨询
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公司原装现货/欢迎来电咨询!
恩XP
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一级代理/放心采购