1. General description

The 74ALVCH162601 is an 18-bit universal transceiver featuring non-inverting 3-state bus

compatible outputs in both send and receive directions. Data flow in each direction is controlled by

output enable (OEAB and OEBA), latch enable (LEAB and LEBA) and clock (CPAB and CPBA)

inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH.

When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is

LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CPAB. When

OEAB is LOW, the outputs are active. When OEAB is HIGH, the outputs are in the high-impedance

state. The clocks can be controlled with the clock-enable inputs (CEBA and CEAB).

Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.

To ensure the high impedance state during power up or power down, OEBA and OEAB should

be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the

current-sinking/current-sourcing capability of the driver.

The 74ALVCH162601 is designed with 30 Ω series resistors in both HIGH or LOW output stage.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

2. Features and benefits

• CMOS low power consumption

• MultiByte flow-through standard pin-out architecture

• Low inductance multiple VCC and GND pins for minimum noise and ground bounce

• Direct interface with TTL levels

• Bus hold on data inputs

• Integrated 30 Ω termination resistors.

• Complies with JEDEC standards:

• JESD8-5 (2.3 V to 2.7 V)

• JESD8B/JESD36 (2.7 V to 3.6 V)

• ESD protection:

• HBM ANSI/ESDA/JEDEC JS-001 exceeds 2000 V

• CDM JESD22-C101E exceeds 1000 V