1. General description

The 74ALVC08 is a quad 2-input AND gate. This device is fully specified for partial power down

applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging

backflow current through the device when it is powered down.

Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times.

2. Features and benefits

• Wide supply voltage range from 1.65 V to 3.6 V

• 3.6 V tolerant inputs/outputs

• CMOS low power consumption

• Direct interface with TTL levels (2.7 V to 3.6 V)

• Power-down mode

• Latch-up performance exceeds 250 mA

• Complies with JEDEC standards:

• JESD8-7 (1.65 V to 1.95 V)

• JESD8-5 (2.3 V to 2.7 V)

• JESD8B (2.7 V to 3.6 V)

• ESD protection:

• MM JESD22-A115-A exceeds 200 V

• HBM JESD22-A114E exceeds 2000 V

• Multiple package options

• Specified from -40 °C to +85 °C