1. General description

The 74AHC595; 74AHCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage

register and 3-state outputs. Both the shift and storage register have separate clocks. The device

features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous

reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH

transitions of the SHCP input. The data in the shift register is transferred to the storage register

on a LOW-to-HIGH transition of the STCP input. If both clocks are connected together, the shift

register will always be one clock pulse ahead of the storage register. Data in the storage register

appears at the output whenever the output enable input (OE) is LOW. A HIGH on OE causes

the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect

the state of the registers. The 74AHCT595 features TTL compatible inputs. Both 74AHC595

and 74AHCT595 inputs are overvoltage tolerant. This feature allows the use of these devices as

translators in mixed voltage environments.

2. Features and benefits

• Wide supply voltage range from 2.0 V to 5.5 V

• Balanced propagation delays

• All inputs have Schmitt-trigger action

• Overvoltage tolerant inputs to 5.5 V

• High noise immunity

• CMOS low power dissipation

• Input levels:

• The 74AHC595 operates with CMOS input levels

• The 74AHCT595 operates with TTL input levels

• ESD protection:

• HBM JESD22-A114F exceeds 2000 V

• MM JESD22-A115-A exceeds 200 V

• CDM JESD22-C101E exceeds 1000 V

• Latch-up performance exceeds 100 mA per JESD 78 Class II Level A

• Multiple package options

• Specified from -40 °C to +85 °C and from -40 °C to +125 °C

3. Applications

• Serial-to-parallel data conversion

• Remote control holding register