TinyLogic짰 UHS Two-Input AND Gate

Description The NC7SZ08 is a single two-input AND gate from Fairchild’s Ultra-High Speed (UHS) series of TinyLogic®. The device is fabricated with advanced CMOS technology to achieve ultra-high speed with high output drive while maintaining low static power dissipation over a broad VCC operatin

TinyLogic UHS Two-Input AND Gate

Description The NC7SZ08 is a single two−input AND gate from onsemi’s Ultra−High Speed (UHS) series of TinyLogic. The device is fabricated with advanced CMOS technology to achieve ultra−high speed with high output drive while maintaining low static power dissipation over a broad VCC operating

TinyLogic® UHS Two-Input AND Gate

Features Ultra-High Speed: tPD 2.7ns (Typical) into 50pF at 5V VCC High Output Drive: ±24mA at 3V VCC Broad VCC Operating Range: 1.65V to 5.5V Matches Performance of LCX Operated at 3.3V VCC Power Down High Impedance Inputs/Outputs Over-Voltage Tolerance inputs facilitate 5V to 3V Tran

封装/外壳：6-UFDFN 包装：卷带（TR） 描述：IC GATE AND 1CH 2-INP 6MICROPAK2 集成电路（IC） 门和反相器

UHS Two-Input AND Gate

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TinyLogic짰 UHS Two-Input AND Gate

Description The NC7SZ08 is a single two-input AND gate from Fairchild’s Ultra-High Speed (UHS) series of TinyLogic®. The device is fabricated with advanced CMOS technology to achieve ultra-high speed with high output drive while maintaining low static power dissipation over a broad VCC operatin

TinyLogic UHS 2-Input AND Gate

General Description The NC7SZ08 is a single 2-Input AND Gate from Fairchild’s Ultra High Speed Series of TinyLogic™. The device is fabricated with advanced CMOS technology to achieve ultra high speed with high output drive while maintaining low static power dissipation over a very broad VCC opera

TinyLogic UHS 2-Input AND Gate

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TinyLogic UHS 2-Input AND Gate

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TinyLogic짰 UHS Two-Input AND Gate

文件：541.91 Kbytes Page：10 Pages

SILICON MONOLITHIC CMOS DIGITAL INTEGRATED CIRCUIT(2-INPUT AND GATE)

The KIC7S08FU is a high speed C2MOS 2-INPUT AND GATE fabricated with silicon gate C2MOS technology. It achieves high speed operation similar to equivalent LSTTL while maintaining the C2MOS low power dissipation. The internal circuit is composed of 2 stages including buffer output, which enables