Input Mux - 2:1 Differential, 1.8 V / 2.5 V, Clock / Data Fanout Buffer - 1:6 CML

The NB7V585M is a differential 1-to-6 CML clock/data distribution chip featuring a 2:1 Clock/Data input multiplexer with an input select pin. The INx/INxb inputs incorporate internal 50-ohm termination resistors and will accept LVPECL, CML, or LVDS logic levels. The NB7V585M produces six identical o • Maximum Input Data Rate > 10 Gb/s Typical\n• Data Dependent Jitter \n• Maximum Input Clock Frequency > 6 GHz Typical\n• Random Clock Jitter \n• Low Skew 1:6 CML Outputs, 30 ps Max\n• 2:1 MultiLevel Mux Inputs\n• 175 ps Typical Propagation Delay\n• 50 ps Typical Rise and Fall Times\n• Operating Ran;

1.8V / 2.5V Differential 2:1 Mux Input to 1:6 CML Clock/Data Fanout Buffer/Translator

文件：156.3 Kbytes Page：8 Pages

1.8V / 2.5V Differential 2:1 Mux Input to 1:6 CML Clock/Data Fanout Buffer/Translator

文件：156.3 Kbytes Page：8 Pages

1.8V / 2.5V Differential 2:1 Mux Input to 1:6 CML Clock/Data Fanout Buffer/Translator

文件：156.3 Kbytes Page：8 Pages

封装/外壳：32-VFQFN 裸露焊盘 包装：管件 描述：IC CLK BUFFER 2:6 7GHZ 32QFN 集成电路（IC） 时钟缓冲器，驱动器