时钟/数据扇出缓冲器，1:4 差分，3 GHz / 2.5 V / 3.3 V，带 LVPECL 输出

The NB6L14 is a 3.0 GHz differential 1:4 LVPECL fanout buffer. The differential inputs incorporate internal 50-ohm termination resistors that are accessed through the VT pin. This feature allows the NB6L14 to accept various logic standards, such as LVPECL, LVCMOS, LVTTL, CML, or LVDS logic levels. T • Input Clock Frequency > 3.0 GHz\n• High performance applications\n• \n• Low Output-to-output skew\n• Internal Input Termination Resistors, 50-ohm\n• No external components needed for inputs\n• VREFAC Reference Output\n• Rebias Capacitor-coupled Input signal;

2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer

文件：153.07 Kbytes Page：10 Pages

2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer

文件：113.36 Kbytes Page：10 Pages

时钟/数据扇出缓冲器，1:4 差分，带 CML 输出

The NB6L14M is a 3.0GHz differential 1:4 CML clock or data fanout buffer. The differential inputs incorporate internal 50-ohm termination resistors that are accessed through the VT pin. This feature allows the NB6L14M to accept various logic standards, such as CML, LVCMOS, LVTTL, CML, or LVDS logic • Input Clock Frequency > 3.0 GHz\n• High performance applications\n• \n• Low Output-to-output skew\n• Internal Input and Output Termination Resistors, 50-ohm\n• No external components needed\n• VREFAC Reference Output\n• Rebias Capacitor-coupled Input Signals;

时钟/数据扇出缓冲器，1:4 AnyLevel™ 输入，LVDS，2.5 V

The NB6L14S is a differential 1:4 Clock or Data Receiver and will accept AnyLevel differential input signals: LVPECL, CML, LVDS, or HCSL. These signals will be translated to LVDS and four identical copies of Clock or Data will be distributed, operating up to 2.0GHz or 2.5Gbps, respectively. As such, • Maximum Input Clock Frequency > 2.0 GHz\n• 1ps Maximum of RMS Clock Jitter\n• VREFAC Reference Output;

2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer

文件：113.36 Kbytes Page：10 Pages

2.5 V/3.3 V 3.0 GHz Differential 1:4 CML Fanout Buffer

文件：154.41 Kbytes Page：11 Pages

2.5 V/3.3 V 3.0 GHz Differential 1:4 CML Fanout Buffer

文件：154.41 Kbytes Page：11 Pages

功能：时钟缓冲器 包装：盒 描述：BOARD EVAL NB6L14MMNG 开发板，套件，编程器 评估和演示板及套件

封装/外壳：16-VFQFN 裸露焊盘 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC CLK BUFFER 1:4 3GHZ 16QFN 集成电路（IC） 时钟缓冲器，驱动器

2.5 V/3.3 V 3.0 GHz Differential 1:4 CML Fanout Buffer

文件：154.41 Kbytes Page：11 Pages

2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer

文件：113.36 Kbytes Page：10 Pages

2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer

文件：153.07 Kbytes Page：10 Pages

2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer

文件：113.36 Kbytes Page：10 Pages

2.5 V/3.3 V 3.0 GHz Differential 1:4 LVPECL Fanout Buffer

文件：153.07 Kbytes Page：10 Pages

2.5 V 1:4 AnyLevel??Differential Input to LVDS Fanout Buffer/Translator

文件：216.58 Kbytes Page：11 Pages

Differential Input to LVDS Fanout Buffer/Translator

文件：241.12 Kbytes Page：11 Pages

Differential Input to LVDS Fanout Buffer/Translator

文件：241.12 Kbytes Page：11 Pages

Differential Input to LVDS Fanout Buffer/Translator

文件：241.12 Kbytes Page：11 Pages

2.5 V 1:4 AnyLevel??Differential Input to LVDS Fanout Buffer/Translator

文件：216.58 Kbytes Page：11 Pages

Differential Input to LVDS Fanout Buffer/Translator

文件：241.12 Kbytes Page：11 Pages

Differential Input to LVDS Fanout Buffer/Translator

文件：241.12 Kbytes Page：11 Pages

2.5 V 1:4 AnyLevel??Differential Input to LVDS Fanout Buffer/Translator

文件：216.58 Kbytes Page：11 Pages