Dual J-K negative edge-triggered flip-flop

DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level

Dual J-K negative edge-triggered flip-flop

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF JK TYPE DUAL 1BIT 16SO 集成电路（IC） 触发器

封装/外壳：16-SOIC（0.154"，3.90mm 宽） 功能：设置（预设）和复位 包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 描述：IC FF JK TYPE DUAL 1BIT 16SO 集成电路（IC） 触发器

Dual J-K negative edge-triggered flip-flop

DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

Dual JK Negative Edge-Triggered Flip-Flop

General Description The 74F112 contains two independent, high-speed JK flip flops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J

Dual JK Negative Edge-Triggered Flip-Flop

文件：83.34 Kbytes Page：7 Pages

Dual JK Negative Edge-Triggered Flip-Flop

文件：83.34 Kbytes Page：7 Pages