Integrated Multiple-Bus Processor

The MC68307 is an integrated processor combining a static 68EC000 processor with multiple interchip bus

interfaces. The MC68307 is designed to provide optimal integration and performance for applications such as digital cordless telephones, portable measuring equipment, and point-of-sale terminals. By providing 3.3 V, static operation in a small package, the MC68307 delivers cost-effective performance to handheld, battery powered applications.

The main features of the MC68307 include:

• Static EC000 Core Processor—Identical to MC68EC000 Microprocessor

— Full compatibility with MC68000 and MC68EC000

— 24-bit address bus, for 16-Mbyte off-chip address space

— 16-bit on-chip data bus for MC68000 bus operations

— Static design allows processor clock to be stopped providing dramatic power savings

— 2.4 MIPS performance at 16.67-MHz processor clock

• External M68000 Bus Interface with Dynamic Bus Sizing for 8-bit and 16-bit Data Ports

• External 8-Bit Data Bus Interface (8051-Compatible)

• M-Bus Module

— Provides interchip bus interface for EEPROMs, LCD controllers, A/D converters, etc.

— Compatible with industry-standard I2C bus

— Master or slave operation modes, supports multiple masters

— Automatic interrupt generation with programmable level

— Software-programmable clock frequency

— Data rates from 4–100 Kbit/s above 3.0-MHz system clock

• Universal Asynchronous Receiver/Transmitter (UART) Module

— Flexible baud rate generator

— Based on MC68681 Dual Universal Asynchronous Receiver/Transmitter (DUART) programming

model

— 5 Mbits/s maximum transfer rate at 16.67-MHz system clock

— Automatic interrupt generation with programmable level

— Modem control signals available (CTS,RTS)

• Timer Module

— Dual channel 16-bit general purpose counter/timer

— Multimode operation, independent capture/compare registers

— Automatic interrupt generation with programmable level

— Third 16-bit timer configured as a software watchdog

— 60-ns resolution at 16.67-MHz system clock

— Each timer has an input and an output pin

• System Integration Module (SIM07), Incorporating Many Functions Typically Relegated to External Pro

grammable Array Logic (PALs), Transistor-Transistor Logic (TTL), and ASICs, such as:

— System configuration, programmable address mapping

— System protection by hardware watchdog logic

— Power-down mode control, programmable processor clock driver

— Four programmable chip selects with wait state generation logic

— Three simple peripheral chip selects

— Parallel input/output ports, some with interrupt capability

— Programmed interrupt vector response for on-chip peripheral modules

— IEEE 1149.1 boundary scan test access port (JTAG)

• Operation from DC to 16.67 MHz (Processor Clock)

• Operating Voltages of 3.3V ±0.3V and 5V ±0.5V

• Compact 100-Lead Quad Flat Pack (QFP) Package