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MC14526BCL中文资料

厂家型号

MC14526BCL

文件大小

286.78Kbytes

页面数量

10

功能描述

Presettable 4-Bit Down Counters

数据手册

下载地址一下载地址二到原厂下载

生产厂商

MOTOROLA

MC14526BCL数据手册规格书PDF详情

Presettable 4-Bit Down Counters

TheMC14522B BCD counter and the MC14526Bbinary counter are constructed with MOS P–channelandN–channel enhancement mode devices in a monolithic structure. Thesedevices are presettable, cascadable, synchronous down counters with a decoded“0” state output for divide–by–N applications. In single stage applicationsthe “0” output is applied to the Preset Enable input. The CascadeFeedback input allows cascade divide–by–N operation with no additionalgates required. The Inhibit inputallows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock.

Thesecomplementary MOS counters can be used in frequency synthesizers,phase–locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• Logic Edge–Clocked Design — Incremented on Positive Transition of Clock or Negative Transition of Inhibit

• Asynchronous Preset Enable

• Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range

更新时间:2025-9-26 16:25:00
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