Introduction

The MC68HC912B32, MC68HC12BE32 and MC68HC(9)12BC32, are 16-bit microcontroller units (MCUs) composed of standard on-chip peripherals. The multiplexed external bus can also operate in an 8-bit narrow mode for interfacing with single 8-bit wide memory in lower-cost systems.

Features

Features include:

• 16-bit CPU12:

– Upwardly compatible with the M68HC11 instruction set

– Interrupt stacking and programmer’s model identical to the M68HC11

– 20-bit arithmetic logic unit (ALU)

– Instruction queue

– Enhanced indexed addressing

– Fuzzy logic instructions

• Multiplexed bus:

– Single chip or expanded

– 16-bit by 16-bit wide or 16-bit by 8-bit narrow modes

• Memory:

– 32-Kbyte FLASH electrically erasable, programmable read-only memory (EEPROM) with 2-Kbyte erase-protected boot block — MC68HC912B32 and MC68HC912BC32 only

– 32-Kbyte ROM — MC68HC12BE32 and MC68HC12BC32 only

– 768-byte EEPROM

– 1-Kbyte random-access memory (RAM) with single-cycle access for aligned or misaligned read/write

• 8-channel, 10-bit analog-to-digital converter (ATD)

• 8-channel standard timer module (TIM) — MC68HC912B32 and MC68HC(9)12BC32 only:

– Each channel fully configurable as either input capture or output compare

– Simple pulse-width modulator (PWM) mode

– Modulus reset of timer counter

• Enhanced capture timer (ECT) — MC68HC12BE32 only:

– 16-bit main counter with 7-bit prescaler

– Eight programmable input capture or output compare channels; four of the eight input captures with buffer

– Input capture filters and buffers, three successive captures on four channels, or two captures on four channels with a capture/compare selectable on the remaining four

– Four 8-bit or two 16-bit pulse accumulators

– 16-bit modulus down-counter with 4-bit prescaler

– Four user-selectable delay counters for signal filtering

• 16-bit pulse accumulator:

– External event counting

– Gated time accumulation

• Pulse-width modulator (PWM):

– 8-bit, 4-channel or 16-bit, 2-channel

– Separate control for each pulse width and duty cycle

– Programmable center-aligned or left-aligned outputs

• Serial interfaces:

– Asynchronous serial communications interface (SCI)

– Synchronous serial peripheral interface (SPI)

– J1850 byte data link communication (BDLC), MC68HC912B32 and MC68HC12BE32 only

– Controller area network (CAN), MC68HC(9)12BC32 only

• Computer operating properly (COP) watchdog timer, clock monitor, and periodic interrupt timer

• Slow-mode clock divider

• 80-pin quad flat pack (QFP)

• Up to 63 general-purpose input/output (I/O) lines

• Single-wire background debug mode (BDM)

• On-chip hardware breakpoints