Description

The V53C317405A is a 4,194,304 x 4 bit highperformance CMOS dynamic random access memory. The V53C317405A offers Page mode operation with Extended Data Output. The V53C317405A has a symmetric address, 11-bit row and 11-bit column.

All inputs are TTL compatible. EDO Page Mode operation allows random access up to 2048 x 4 bits, within a page, with cycle times as short as 20ns.

These features make the V53C317405A ideally suited for a wide variety of high performance computer systems and peripheral applications.

Features

■ 4M x 4-bit organization

■ EDO Page Mode for a sustained data rate of 50 MHz

■ RAS access time: 50, 60, 70 ns

■ Low power dissipation

■ Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh, Hidden Refresh

■ Refresh Interval: 2048 cycles/32 ms

■ Available in 24/26-pin 300 mil SOJ, and 24/26-pin 300 mil TSOP-II

■ Single +3.3 V ±10 Power Supply

■ TTL Interface