位置:MH8V7245BAZTJ-6 > MH8V7245BAZTJ-6详情

MH8V7245BAZTJ-6中文资料

厂家型号

MH8V7245BAZTJ-6

文件大小

147.26Kbytes

页面数量

23

功能描述

HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM

数据手册

下载地址一下载地址二到原厂下载

生产厂商

MITSUBISHI

MH8V7245BAZTJ-6数据手册规格书PDF详情

DESCRIPTION

The MH8V7245BAZTJ is 8388608-word x 72-bit dynamic ram module. This consist of nine industry standard 8M x 8 dynamic RAMs in TSOP and three industry standard input buffer in TSSOP.

The mounting of TSOP on a card edge dual in-line package provides any application where high densities and large of quantities memory are required.

This is a socket-type memory module ,suitable for easy interchange or addition of module.

FEATURES

• Utilizes industry standard 8M x 8 RAMs in TSOP and industry standard input buffer in TSSOP

• 168-pin (84-pin dual dual in-line package)

• Single +3.3V(±0.3V) supply operation

• Low stand-by power dissipation

116.2mW(Max) . . . . . . . . . . LVCMOS input level

• Low operation power dissipation

MH8V7245BAZTJ -5 . . . . . . . . . . . . . . . . . . 4.32W(Max)

MH8V7245BAZTJ -6 . . . . . . . . . . . . . . . . . . 4.00W(Max)

• All input are directly LVTTL compatible

• All output are three-state and directly LVTTL compatible

• Includes(0.22uF x 11) decoupling capacitors

• 4096 refresh cycle every 64ms (A0~11)

• Hyper-page mode,Read-modify-write, /CAS before /RAS refresh,Hidden refresh capabilities

• JEDEC standard pin configuration & Buffered PD pin

• Buffered input except /RAS and DQ

• Gold plating contact pads

APPLICATION

Main memory unit for computers , Microcomputer memory

更新时间:2025-8-14 9:03:00
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