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M2S56D30ATP-10L中文资料

厂家型号

M2S56D30ATP-10L

文件大小

824.58Kbytes

页面数量

37

功能描述

256M Double Data Rate Synchronous DRAM

数据手册

下载地址一下载地址二到原厂下载

生产厂商

MITSUBISHI

M2S56D30ATP-10L数据手册规格书PDF详情

DESCRIPTION

M2S56D20AKT is a 4-bank x 16,777,216-word x 4-bit,

M2S56D30AKT is a 4-bank x 8,388,608-word x 8-bit,

M2S56D40AKT is a 4-bank x 4,194,304-word x 16-bit,

double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. The M2S56D20/30/40AKT achieves very high speed data rate up to 133MHz, and are suitable for main memory in computer systems.

FEATURES

- Vdd=Vddq=2.5V+0.2V

- Double data rate architecture; two data transfers per clock cycle

- Bidirectional, data strobe (DQS) is transmitted/received with data

- Differential clock inputs (CLK and /CLK)

- DLL aligns DQ and DQS transitions with CLK transitions edges of DQS

- Commands entered on each positive CLK edge;

- data and data mask referenced to both edges of DQS

- 4 bank operation controlled by BA0, BA1 (Bank Address)

- /CAS latency- 2.0/2.5 (programmable)

- Burst length- 2/4/8 (programmable)

- Burst type- sequential / interleave (programmable)

- Auto precharge / All bank precharge controlled by A10

- 8192 refresh cycles /64ms (4 banks concurrent refresh)

- Auto refresh and Self refresh

- Row address A0-12 / Column address A0-9,11(x4)/ A0-9(x8)/ A0-8(x16)

- SSTL_2 Interface

- 400-mil, 66-pin Thin Small Outline Package (TSOP II)

- JEDEC standard

更新时间:2025-10-19 11:00:00
供应商 型号 品牌 批号 封装 库存 备注 价格
MIT
23+
TSOP
50000
全新原装正品现货,支持订货
MIT
24+
NA/
605
优势代理渠道,原装正品,可全系列订货开增值税票
A
23+
TSOP
13000
原厂授权一级代理,专业海外优势订货,价格优势、品种
MIT
25+
TSOP
3200
十年品牌!原装现货!!!
24+
3000
公司存货
MIT
02+
TSOP
60
原装现货海量库存欢迎咨询
MIT
23+
TSOP
8650
受权代理!全新原装现货特价热卖!
MIT
25+
QFP
3200
全新原装、诚信经营、公司现货销售!
MIT
TSOP
68500
一级代理 原装正品假一罚十价格优势长期供货
MIT
2402+
TSOP
8324
原装正品!实单价优!