Features

• Ultra-low-voltage core and I/O power supplies

• Frequency range

– 400 MHz (data rate: 800 Mb/s/pin)

• 4n prefetch DDR architecture

• 8 internal banks for concurrent operation

• Multiplexed, double data rate, command/address

inputs; commands entered on each CK_t/CK_c

edge

• Bidirectional/differential data strobe per byte of

data (DQS_t/DQS_c)

• Programmable READ and WRITE latencies (RL/WL)

• Burst length: 4, 8, and 16

• Per-bank refresh for concurrent operation

• Auto temperature-compensated self refresh

(ATCSR) by built-in temperature sensor

• Partial-array self refresh (PASR)

• Deep power-down mode (DPD)

• Selectable output drive strength (DS)

• Clock-stop capability

• Lead-free (RoHS-compliant) and halogen-free

packaging

Options Marking

• Density/Chip select

– 8Gb/2-CS - dual die 81

• Organization

– x32 32

• VDD1/VDD2/VDDQ: 1.8V/1.2V/1.2V B

• Revision 4

• FBGA “green” package

– 12mm x 12mm x 0.8mm, 168-ball PB

• Timing – cycle time

– 2.5ns @ RL = 6 -8D

• Operating temperature range

– From –30°C to +85°C Blank