Operating Conditions (PIC32CX SG41)

• 1.71V - 3.63V, -40°C to +85°C, DC to 120 MHz

• 1.71V - 3.63V, -40°C to +125°C, DC to 100 MHz

Operating Conditions (PIC32CX SG60/SG61)

• 2.7V - 3.63V, -40°C to +85°C, DC to 120 MHz

• 2.7V - 3.63V, -40°C to +125°C, DC to 100 MHz

Core:

• Arm® Cortex®-M4F CPU running at up to 120 MHz:

– 403 CoreMark® at 120 MHz

– 4 KB combined instruction cache and data cache

– 8-Zone Memory Protection Unit (MPU)

– Thumb®-2 instruction set

– Embedded Trace Module (ETM) with instruction trace stream

– CoreSight Embedded Trace Buffer (ETB)

– Trace Port Interface Unit (TPIU)

– Floating Point Unit (FPU)

Memories

• 1 MB in-system self-programmable Flash with:

– Error Correction Code (ECC)

– Dual bank with Read-While-Write (RWW) support

– EEPROM hardware emulation

• 256 KB SRAM main memory

– 128 KB with Error Correction Code (ECC) RAM option

• Up to 4 KB of Tightly Coupled Memory (TCM)

• 8 KB additional SRAM

– Can be retained in backup mode

• Eight 32-bit backup registers

Low-Power and Power Management

• Idle, Standby, Hibernate, Backup, and Off sleep modes

• SleepWalking peripherals

• Battery backup support

• Embedded Buck/LDO regulator supporting on-the-fly selection

I/O

• Up to 99 programmable I/O pins

Security and Safety

• One Advanced Encryption System (AES) with 256-bit key length

and up to 2 MB/s data rate

– ECB, CBC, CFB, OFB, CTR modes of operation

– Supports counter with CBC-MAC mode

– Galois Counter Mode (GCM)

• True Random Number Generator (TRNG)

• Public Key Cryptography Controller (PUKCC) and associated

Classical Public Key Cryptography Library (PUKCL)

– RSA, DSA

– Elliptic Curves Cryptography (ECC) ECC GF(2n), ECC GF(p)

• Integrity Check Module (ICM) based on Secure Hash Algorithm

(SHA1, SHA224, SHA256), DMA assisted

• Permanent protection against Chip Erase, Boot section

Programming and Debug access, allowing Immutable Boot

(optional)

• Size-configurable Immutable Boot section in Flash with Boot

Read Protection, allowing secure boot support (optional)

Hardware Security Module (optional)

• Secure boot support: Validation of host code image and host

code signature validation

• Secure update support for host code: Secure encryption key

storage and image decryption

• X.509 Certificate storage, parsing, validation and revocation,

supporting both ECC and RSA

• High-speed SHA256, HMAC and AES-CMAC engines

• P224, P256 and P384 Elliptic Curve – ECDSA Sign/Verify

• ECDH support for P256 & P224 Curves

• ECBD support for P224 Curve

• SECP256K1 (Bitcoin/Blockchain curve) ECDSA support

• 256-bit Brainpool Elliptic Curve support – ECDSA, ECDH

• RSA - 2048 Sign/Verify, 3072 Verify, 1024 Encrypt/Decrypt

• 256 bit key generation and derivation

• 2048 bit RSA key generation and derivation

• Elliptic Curve Diffie Hellman (ECDH/ECDHE) Key Agreement

• NIST SP800-90 Random Number Generator (RNG)

• Internal symmetric and asymmetric key generation

Peripherals

• 32-channel Event System

• Eight Serial Communication Interfaces (SERCOM), each

configurable to operate as either:

– USART with full-duplex and single-wire half-duplex

configuration

– ISO7816

– I2C up to 3.4 MHz

– SPI with optional inter-byte space

– LIN host/client

– RS485

– Hardware Security Module interface (optional)

• Eight 16-bit Timers/Counters (TC) each configurable as:

– 16-bit TC with two compare/capture channels

– 8-bit TC with two compare/capture channels

– 32-bit TC with two compare/capture channels, by pairing two

TCs

• Two 24-bit Timer/Counters for Control (TCC), with extended

functions:

– Up to six compare channels with optional complementary

output

– Generation of synchronized pulse width modulation (PWM)

pattern across port pins

– Deterministic fault protection, fast decay and configurable

dead-time between complementary output

– Dithering increasing resolution with up to 5 bit and reducing

quantization error

• Three 16-bit Timer/Counters for Control (TCC) with extended

functions:

– Up to three compare channels with optional complementary

output

• 32-bit Real Time Counter (RTC) with clock/calendar function

• Up to 5 wake-up pins with tamper detection and debouncing filter

• Watchdog Timer (WDT) with Window mode

• CRC-32 generator

• One two-channel Inter-IC Sound Interface (I2S)

• Position Decoder (PDEC)

• Frequency meter (FREQM)

• Four Configurable Custom Logic (CCL)

• Dual 12-bit, 1 Msps ADC with up to 16 channels each:

– Differential and single-ended input

– Automatic offset and gain error compensation

– Oversampling and decimation in hardware to support 13-bit,

14-bit, 15-bit, or 16-bit resolution

Peripherals continued...

• Dual 12-bit, 1 Msps output DAC

• Two Analog Comparators (AC) with Window Compare function

• Parallel Capture Controller (PCC), up to 14 bits wide

• Peripheral Touch Controller (PTC)

– Capacitive Touch buttons, sliders, and wheels

– Wake-up on touch

– Up to 32 self-capacitance and up to 256 mutualcapacitance

channels

High-Performance Peripherals

• 32-channel Direct Memory Access Controller (DMAC)

– Built-in CRC with memory CRC generation/monitor

hardware support

• Two SD/MMC Host Controller (SDHC)

– Up to 50 MHz operation

– 4-bit or 1-bit interface

– Compatibility with SD and SDHC memory card specification

version 3.01

– Compatibility with SDIO specification version 3.0

– Compliant with JDEC specification, MMC memory cards

V4.51

• One Quad I/O Serial Peripheral Interface (QSPI)

– eXecute-In-Place (XIP) support

– Dedicated AHB memory zone

• One Ethernet MAC

– 10/100 Mbps with dedicated DMA

– IEEE® 1588 Precision Time Protocol (PTP) support

– IEEE 1588 Time Stamping Unit (TSU) support

– IEEE802.3AZ energy efficiency support

– Support for 802.1AS and 1588 precision clock

synchronization protocol

– Wake on LAN support

• Two Controller Area Network (CAN)

– Support for CAN 2.0A/CAN 2.0B and CAN-FD (ISO

11898-1:2015)

• One Full-Speed (12 Mbps) Universal Serial Bus (USB) 2.0

interface

– Embedded host and device function

– Eight endpoints

– On-chip transceiver with integrated serial resistor

System

• Power-on Reset (POR) and Brown-out Detection (BOD)

• Internal and external clock options

• External Interrupt Controller (EIC)

• 16 external interrupts

• One non-maskable interrupt

Clock Management

• 32.768 kHz crystal oscillator (XOSC32K) with Clock failure

detection

• Two 8 MHz to 48 MHz crystal oscillator (XOSC) with Clock failure

detection

• 32.768 kHz ultra low-power internal oscillator (OSCULP32K)

• 48 MHz Digital Frequency Locked Loop (DFLL48M)

• Two 96-200 MHz Fractional Digital Phased Locked Loop

(FDPLL200M)

Software and Tools Support: Develop Prototypes Quickly With A

Powerful, Easy-to-Use Ecosystem

• Get the code off to a head start with MPLAB® Code Configurator

• Graphically configure peripherals, software libraries, and

supported RTOS with MPLAB Harmony

• Download MPLAB XC Compiler

• Take advantage of MPLAB X IDE's support for 32-bit MCUs

• Select the best debugger for the project: MPLAB ICE, ICD, or

PICkit™

Debugger Development Support

• Two-pin Serial Wire Debug (SWD) programming and debugging

interface

• Six hardware breakpoints and four data watchpoints