High-Performance CPU

• Modified Harvard Architecture

• 64 Kbytes of Flash Memory

• 8 Kbytes of SRAM

• Up to 16 MIPS Operation @ 32 MHz

• 8 MHz Fast RC (FRC) Internal Oscillator:

– 96 MHz PLL option

– Multiple clock divide options

– Fast start-up

• 17-Bit x 17-Bit Single-Cycle Hardware Fractional/Integer Multiplier

• 32-Bit by 16-Bit Hardware Divider

• 16-Bit x 16-Bit Working Register Array

• C Compiler Optimized Instruction Set Architecture

• Two Address Generation Units (AGUs) for Separate Read and Write Addressing of Data Memory