High-Performance RISC CPU:

• C Compiler Optimized Architecture:

- Optional extended instruction set designed to optimize re-entrant code

• Up to 1024 bytes Data EEPROM

• Up to 64 Kbytes Linear Program Memory Addressing

• Up to 3936 bytes Linear Data Memory Addressing

• Up to 16 MIPS Operation

• 16-bit Wide Instructions, 8-bit Wide Data Path

• Priority Levels for Interrupts

• 31-Level, Software Accessible Hardware Stack

• 8 x 8 Single-Cycle Hardware Multiplier