Features

• High-Density, High-Performance, Electrically-

Erasable Complex Programmable Logic

Device:

- 3.0V to 3.6V operating range

- 64 macrocells

- 5 product terms per macrocell, expandable

up to 40 per macrocell

- 44 and 100 pins

- 15 ns maximum pin-to-pin delay

- Registered operation up to 77 MHz

- Enhanced routing resources

• In-System Programmability (ISP) via JTAG

• Flexible Logic Macrocell:

- D/T/Latch configurable flip-flops

- Global and individual register control signals

- Global and individual output enable

- Programmable output slew rate

- Programmable output open-collector option

- Maximum logic utilization by burying a register

with a COM output

• Advanced Power Management Features:

- Automatic 5 μA Standby (ATF1504ASVL)

- Pin-controlled 100 μA Standby mode (typical)

- Programmable pin-keeper circuits on inputs

and I/Os

- Reduced-power feature per macrocell

• Available in Industrial Temperature Range

• Robust EEPROM Technology:

- 100 tested

- Completely reprogrammable

- 10,000 Program/Erase cycles

- 20-year data retention

- 2000V ESD protection

- 200 mA latch-up immunity

• JTAG Boundary-Scan Testing to IEEE Std.

1149.1-1990 and 1149.1a-1993 Supported

• PCI-Compliant

• Security Fuse Feature

• Green (Pb/Halide-Free/RoHS Compliant)

Package Options